Process for self-align contact

Claim 2

A self-aligned contact connecting conductive lines to active regions in a silicon substrate, comprising: a first insulating layer over said silicon substrate, with openings over said active regions; a barrier metal layer over said active regions, along surfaces of said openings, and over a portion of the horizontal surfaces of said first insulating layer in the region adjacent to said openings; a refractory metal layer over said barrier metal layer; conductive lines self-aligned over said barrier metal layer and over said refractory metal layer; and sidewall spacers adjacent to said conductive lines and over those regions of said refractory metal layer not covered by said conductive lines.

Claim 3

The self-aligned contact of claim 1 wherein said refractory metal layer is tungsten, having a thickness of between about 2000 and 10,000 Angstroms.

Claim 4

The self-aligned contact of claim 1 wherein said barrier metal layer has a thickness of between about 300 and 1500 Angstroms.

Claim 5

The self-aligned contact of claim 3 wherein said barrier metal layer is titanium tungsten.

Claim 6

The self-aligned contact of claim 3 wherein said barrier metal layer is titanium/titanium nitride.

Claim 7

The self-aligned contact of claim 1 wherein said conductive lines are aluminum.

Claim 8

The self-aligned contact of claim 1 wherein said openings have a width of between about 0.25 and 1.0 micrometers.

Claim 9

The self-aligned contact of claim 1 wherein said sidewall spacers are silicon oxide and have a width of between about 0.2 and 0.5 micrometers.

Claim 12

The method of claim 9 wherein said refractory metal layer is formed of tungsten, and is formed to a thickness of between about 2000 and 10,000 Angstroms.

Claim 13

The method of claim 9 wherein said barrier metal layer is formed to a thickness of between about 300 and 1500 Angstroms.

Claim 14

The method of claim 11 wherein said barrier metal layer is formed of titanium tungsten.

Claim 15

The method of claim 11 wherein said barrier metal layer is formed of titanium/titanium nitride.

Claim 16

The method of claim 9 wherein said conductive lines are formed of aluminum.

Claim 17

The method of claim 9 wherein said openings are formed to a width of between about 0.25 and 1.0 micrometers.

Claim 18

The method of claim 9 wherein said forming insulating spacer sidewalls comprises the steps of: depositing an oxide layer over said conductive lines and exposed surface of said refractory metal layer; and anisotropically etching said oxide layer to remove material from the horizontal surfaces of said conductive lines and said refractory metal layer, and to leave said insulating spacer sidewalls adjacent to said conductive lines.

Claim 19

The method of claim 16 wherein said oxide layer is formed to a thickness of between about 2000 and 5000 Angstroms.

Claim 20

An integrated circuit with a metallization system of conductive lines in self-aligned contact to the active regions of field effect transistor (FET) devices, comprising: said field effect transistor devices formed in and on a silicon substrate, isolated from other of said field effect transistor devices by field oxide regions, having said active regions, gate oxide between said active regions, and a gate over said gate oxide; a first insulating layer over said field effect transistor, with openings in said first insulating layer over said active regions; a barrier metal layer over said active regions, along surfaces of said openings, and over a portion of the horizontal surfaces of said first insulating layer in the region adjacent to said openings; a refractory metal layer over said barrier metal layer; conductive lines self-aligned over said barrier metal layer and over said refractory metal layer; and sidewall spacers adjacent to said conductive lines and over those regions of said refractory metal layer not covered by said conductive lines.

Claim 21

An integrated circuit with a metallization system of conductive lines in self-aligned contact to the active regions of field effect transistor (FET) devices, comprising: said field effect transistor devices formed in and on a silicon substrate, isolated from other of said field effect transistor devices by field oxide regions, having said active regions, gate oxide between said active regions, and a gate over said gate oxide; a first insulating layer over said field effect transistor, with openings in said first insulating layer over said active regions; a barrier metal layer over said active regions, along surfaces of said openings, and over a portion of the horizontal surfaces of said first insulating layer in the region adjacent to said openings; a refractory metal layer over said barrier metal layer; conductive lines self-aligned over said barrier metal layer and over said refractory metal layer; and sidewall spacers adjacent to said conductive lines and over those regions of said refractory metal layer not covered by said conductive lines.

Claim 22

The integrated circuit of claim 18 wherein said refractory metal layer is tungsten, having a thickness of between about 2000 and 10,000 Angstroms.

Claim 23

The integrated circuit of claim 18 wherein said barrier metal layer has a thickness of between about 300 and 1500 Angstroms.

Claim 24

The integrated circuit of claim 20 wherein said barrier metal layer is titanium tungsten.

Claim 25

The integrated circuit of claim 20 wherein said barrier metal layer is titanium/titanium nitride.

Claim 26

The integrated circuit of claim 18 wherein said conductive lines are aluminum.

Claim 27

The integrated circuit of claim 18 wherein said sidewall spacers are silicon oxide and have a width of between about 0.2 and 0.5 micrometers.

Claim 28

The integrated circuit of claim 18 wherein said conductive lines may be formed in subsequent metallization layers in self-aligned contact with conductive lines in the preceding layer.