Method of forming a dram cell having a ring-type stacked capacitor

Claim 1

A method for fabricating a high capacitance stacked capacitor on a semiconductor substrate having a device areas formed therein and a field oxide elsewhere on said substrate, comprising the steps of: providing a field effect transistor structure in and on said device area on said semiconductor substrate; said field effect transistor having a gate electrode patterned from a first polysilicon layer with a first insulating layer and insulating sidewall spacers thereon and having source/drain areas in and on said device area and adjacent to said gate electrode; depositing a second insulating layer on said device areas and elsewhere over said substrate; using a photoresist mask and etching self-aligning contact openings in said second insulating layer to one of two said source/drain areas of said field effect transistor; depositing a second polysilicon layer on said substrate and contacting said source/drain in said opening; patterning said second polysilicon layer having portions remaining over said self-aligned contact and forming a bottom capacitor electrode making contact to said source/drain area; using said same photoresist mask of said contact openings to pattern and partially etch said bottom capacitor electrode forming ring-type sidewalls on said bottom capacitor electrode; doping with impurities said bottom capacitor electrode by implantation and thereby increasing the conductivity and forming ohmic contact to said source/drain area; forming a capacitor dielectric layer on surface of said bottom capacitor electrode; depositing a third polysilicon layer on said substrate and patterning to form a top capacitor electrode and completing said stacked capacitor.

Claim 2

A method for fabricating a high capacitance stacked capacitor on a semiconductor substrate having a device areas formed therein and a field oxide elsewhere on said substrate, comprising the steps of: providing a field effect transistor structure in and on said device area on said semiconductor substrate; said field effect transistor having a gate electrode patterned from a first polysilicon layer with a first insulating layer and insulating sidewall spacers thereon and having source/drain areas in and on said device area and adjacent to said gate electrode; depositing a second insulating layer on said device areas and elsewhere over said substrate; using a photoresist mask and etching self-aligning contact openings in said second insulating layer to one of two said source/drain areas of said field effect transistor; depositing a second polysilicon layer on said substrate and contacting said source/drain in said opening; patterning said second polysilicon layer having portions remaining over said self-aligned contact and forming a bottom capacitor electrode making contact to said source/drain area; using said same photoresist mask of said contact openings to pattern and partially etch said bottom capacitor electrode forming ring-type sidewalls on said bottom capacitor electrode; doping with impurities said bottom capacitor electrode by implantation and thereby increasing the conductivity and forming ohmic contact to said source/drain area; forming a capacitor dielectric layer on surface of said bottom capacitor electrode; depositing a third polysilicon layer on said substrate and patterning to form a top capacitor electrode and completing said stacked capacitor.

Claim 13

A method for fabricating a dynamic random access memory having an array of high capacitance stacked capacitor on a semiconductor substrate comprising the steps of: forming a patterned relatively thick field oxide on the principle surface of a semiconductor substrate while leaving device for fabrication of field effect transistors; forming a gate oxide layer on said substrate in said device areas; depositing a first polysilicon layer on said substrate; depositing a first insulating layer on said first polysilicon layer; and patterning said first insulating layer and first polysilicon layer forming .gate electrodes structures in said device areas and patterned conducting layers elsewhere on said field oxide areas; forming source/drain areas adjacent to and on both sides of said gate electrode structures; and forming insulating sidewall spacers on said gate electrode structures and on said patterned conducting layers; and then forming said stacked capacitor by, depositing a second insulating layer on said device areas and elsewhere over said substrate, etching self-aligning contact openings in said second insulating layer to one of said two source/drain areas of said field effect transistors using a photoresist mask, depositing a second polysilicon layer on said substrate and contacting said source/drain areas in said contact openings, patterning said second polysilicon layer having portions remaining over said self-aligned contact and forming a bottom capacitor electrodes making contact to said source/drain areas, using said same photoresist mask of said contact openings to pattern and partially etch said bottom capacitor electrode forming ringed sidewalls on said bottom capacitor electrode, doping with impurities said bottom capacitor electrode by implantation, and thereby increasing the conductivity, and forming ohmic contact to said source/drain area, forming a capacitor dielectric layer on surface of said bottom capacitor electrode, depositing and patterning a third polysilicon layer over said capacitor dielectric layer on said substrate and forming a top capacitor electrode and completing said stacked capacitor.

Claim 14

A method for fabricating a dynamic random access memory having an array of high capacitance stacked capacitor on a semiconductor substrate comprising the steps of: forming a patterned relatively thick field oxide on the principle surface of a semiconductor substrate while leaving device for fabrication of field effect transistors; forming a gate oxide layer on said substrate in said device areas; depositing a first polysilicon layer on said substrate; depositing a first insulating layer on said first polysilicon layer; and patterning said first insulating layer and first polysilicon layer forming .gate electrodes structures in said device areas and patterned conducting layers elsewhere on said field oxide areas; forming source/drain areas adjacent to and on both sides of said gate electrode structures; and forming insulating sidewall spacers on said gate electrode structures and on said patterned conducting layers; and then forming said stacked capacitor by, depositing a second insulating layer on said device areas and elsewhere over said substrate, etching self-aligning contact openings in said second insulating layer to one of said two source/drain areas of said field effect transistors using a photoresist mask, depositing a second polysilicon layer on said substrate and contacting said source/drain areas in said contact openings, patterning said second polysilicon layer having portions remaining over said self-aligned contact and forming a bottom capacitor electrodes making contact to said source/drain areas, using said same photoresist mask of said contact openings to pattern and partially etch said bottom capacitor electrode forming ringed sidewalls on said bottom capacitor electrode, doping with impurities said bottom capacitor electrode by implantation, and thereby increasing the conductivity, and forming ohmic contact to said source/drain area, forming a capacitor dielectric layer on surface of said bottom capacitor electrode, depositing and patterning a third polysilicon layer over said capacitor dielectric layer on said substrate and forming a top capacitor electrode and completing said stacked capacitor.