Patent US5428304A successfully refreshed from Google Patents.
US5428304A
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Programmable gate array with special interconnects for adjacent gates and isolation devices used during programming
Assignee: Texas Instruments Inc
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Filing: 1994-07-08
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Granted: 1995-06-27
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Expires: 2014-07-08
Abstract
Abstract Programmable circuitry (10) is provided including a plurality of logic modules (12) each having at least one input conductor (16). A nearest neighbor conductor (36) is fusibly coupled to output circuitry (25) of a selected logic module (12), the nearest neighbor conductor (36) intersecting the input conductor (16) of a nearest neighbor logic module (12). A fuse (40) disposed at the intersection of the nearest neighbor conductor (36) and the input conductor (16) of the nearest neighbor logic module (12) is provided for selectively establishing electrical coupling therebetween.
Inventors
- 👤 Robert J. Landers
- 👤 Mark G. Harward
- 👤 Jeffrey A. Niehaus
- 👤 Daniel D. Edmonson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
277 words
A programmable logic array comprising: a plurality of output connection leads running the length of said array; a plurality of input connection leads running the length of said array and disposed in parallel to said output connection leads; a plurality of interconnection leads running the width of said array and disposed perpendicularly to said output and input connection leads; a first plurality of programmable links at the intersection of said output and input connection leads with said interconnection leads; a plurality of logic elements arranged in rows and columns, each of said logic elements including: a plurality of input leads, at least one high capacity output lead connected to a high capacity output driver, said high capacity output driver having sufficient current driving capability to drive at least one of said output connection leads or said interconnection leads; and at least one low capacity output lead connected to a low capacity output driver, said low capacity output driver having a current driving capability less than that of said high capacity output driver; a second plurality of programmable links at the intersection of said input leads of said logic elements and said input connection leads; a third plurality of programmable links at the intersection of said high capacity output lead of said logic elements and said output connection leads; at least one local interconnection lead extending from said low capacity output lead of a first logic element to the input leads of a second of said logic elements; and a fourth plurality of programmable links at the intersection of said local interconnection lead and said low capacity output lead and said input leads of said second logic element.
Claim 2
Dependent Claim
277 words
A programmable logic array comprising: a plurality of output connection leads running the length of said array; a plurality of input connection leads running the length of said array and disposed in parallel to said output connection leads; a plurality of interconnection leads running the width of said array and disposed perpendicularly to said output and input connection leads; a first plurality of programmable links at the intersection of said output and input connection leads with said interconnection leads; a plurality of logic elements arranged in rows and columns, each of said logic elements including: a plurality of input leads, at least one high capacity output lead connected to a high capacity output driver, said high capacity output driver having sufficient current driving capability to drive at least one of said output connection leads or said interconnection leads; and at least one low capacity output lead connected to a low capacity output driver, said low capacity output driver having a current driving capability less than that of said high capacity output driver; a second plurality of programmable links at the intersection of said input leads of said logic elements and said input connection leads; a third plurality of programmable links at the intersection of said high capacity output lead of said logic elements and said output connection leads; at least one local interconnection lead extending from said low capacity output lead of a first logic element to the input leads of a second of said logic elements; and a fourth plurality of programmable links at the intersection of said local interconnection lead and said low capacity output lead and said input leads of said second logic element.
Claim 3
Dependent Claim
16 words
A programmable logic array as in claim 1 wherein said logic elements comprise programmable logic elements.
Claim 4
Dependent Claim
15 words
A programmable logic array as in claim 1 wherein said programmable links are fusible links.
Claim 5
Dependent Claim
20 words
A programmable logic array as in claim 1 wherein said second logic element is adjacent to said first logic element.
Claim 6
Dependent Claim
27 words
A programmable logic array as in claim 1 wherein said second logic element is within a selected number of logic elements away from said first logic element.
Claim 7
Dependent Claim
390 words
A programmable logic array comprising: a plurality of output connection leads running the length of said array; a plurality of input connection leads running the length of said array and disposed in parallel to said output connection leads; a plurality of interconnection leads running the width of said array and disposed perpendicularly to said output and input connection leads; a first plurality of programmable links at the intersection of said output and input connection leads with said interconnection leads; a plurality of logic elements arranged in rows and columns, each of said logic elements including: a plurality of input leads, at least one high capacity output lead connected to a high capacity output driver, said high capacity output driver having sufficient current driving capability to drive at least one of said output connection leads or said interconnection leads; and at least one low capacity output lead connected to a low capacity output driver, said low capacity output driver having a current driving capability less than that of said high capacity output driver; a second plurality of programmable links at the intersection of said input leads of said logic elements and said input connection leads; a third plurality of programmable links at the intersection of said high capacity output lead of said logic elements and said output connection leads; at least one local interconnection lead extending from said low capacity output lead of a first logic element to the input leads of a second of said logic elements, said interconnection lead being connected to an addressable source of programming voltage; a fourth plurality of programmable links at the intersection of said local interconnection lead and said low capacity output lead and said input leads of said second logic element; and a plurality of addressing signals provided to said addressable source of programming voltage, said low capacity output lead and a selected input lead of said second logic element, said addressing signals causing said programming voltage to be applied to said interconnection lead and causing said low capacity output lead and said selected input lead of said second logic element to be connected to a reference potential thus causing the programmable links of said fourth plurality of programmable links between said local interconnection lead, said low capacity output lead and said selected input lead of said second logic element to become conductive.
Claim 8
Dependent Claim
390 words
A programmable logic array comprising: a plurality of output connection leads running the length of said array; a plurality of input connection leads running the length of said array and disposed in parallel to said output connection leads; a plurality of interconnection leads running the width of said array and disposed perpendicularly to said output and input connection leads; a first plurality of programmable links at the intersection of said output and input connection leads with said interconnection leads; a plurality of logic elements arranged in rows and columns, each of said logic elements including: a plurality of input leads, at least one high capacity output lead connected to a high capacity output driver, said high capacity output driver having sufficient current driving capability to drive at least one of said output connection leads or said interconnection leads; and at least one low capacity output lead connected to a low capacity output driver, said low capacity output driver having a current driving capability less than that of said high capacity output driver; a second plurality of programmable links at the intersection of said input leads of said logic elements and said input connection leads; a third plurality of programmable links at the intersection of said high capacity output lead of said logic elements and said output connection leads; at least one local interconnection lead extending from said low capacity output lead of a first logic element to the input leads of a second of said logic elements, said interconnection lead being connected to an addressable source of programming voltage; a fourth plurality of programmable links at the intersection of said local interconnection lead and said low capacity output lead and said input leads of said second logic element; and a plurality of addressing signals provided to said addressable source of programming voltage, said low capacity output lead and a selected input lead of said second logic element, said addressing signals causing said programming voltage to be applied to said interconnection lead and causing said low capacity output lead and said selected input lead of said second logic element to be connected to a reference potential thus causing the programmable links of said fourth plurality of programmable links between said local interconnection lead, said low capacity output lead and said selected input lead of said second logic element to become conductive.
Claim 9
Dependent Claim
16 words
A programmable logic array as in claim 6 wherein said logic elements comprise programmable logic elements.
Claim 10
Dependent Claim
15 words
A programmable logic array as in claim 6 wherein said programmable links are fusible links.
Claim 11
Dependent Claim
20 words
A programmable logic array as in claim 6 wherein said second logic element is adjacent to said first logic element.
Claim 12
Dependent Claim
27 words
A programmable logic array as in claim 6 wherein said second logic element is within a selected number of logic elements away from said first logic element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |