Interference compensating circuit including a matched filter followed by a median filter

Claim 2

A received signal filtering circuit arrangement, the circuit arrangement having an input for receiving a data signal in conjunction with an interference signal and comprising a matched filter, said circuit arrangement being characterized in that the output of the matched filter is coupled to an input of a median filter to compensate for rapid impulses in the data signal, and an output of the median filter is coupled to further circuit means in which a signal characteristic of an interference signal at the output of the matched filter is determined.

Claim 3

A circuit arrangement as claimed in claim 1, wherein the output of the matched filter is coupled to the further circuit means through a delay means.

Claim 4

A circuit arrangement as claimed in claim 2, wherein the delay means delays the output signal from the matched filter by "k" samples prior to being supplied to the the further circuit means, where k is an integer.

Claim 5

A circuit arrangement as claimed in claim 2, wherein a difference between an output of the delay means, and the output of the median filter, is calculated to provide an output signal having a magnitude that is a function of a magnitude of the interference signal.

Claim 6

A circuit arrangement as claimed in claim 2, wherein the circuit arrangement comprises an adder means interposed between said further circuit means and both of said matched filter/delay means and said median filter, said adder means having a first input coupled to an output of said delay means, a second input coupled to said output of said median filter, and an output coupled to an input of said further circuit means, said output of said adder means expressing a difference between the delayed signal at said first input and the median filtered signal at said second input.

Claim 7

A circuit arrangement as claimed in claim 2, wherein the signal or samples obtained from the matched filter are filtered in the median filter so that a median of 2k+1 samples is calculated, where k is an integer, and that at substantially the same time the samples obtained at the output of the matched filter are delayed by k samples in the delay means.

Claim 8

A circuit arrangement as claimed in claim 2, wherein the delayed signal is supplied to a decision circuit, the output of the median filter is supplied to a calculation circuit, which calculates a threshold value and then supplies the calculated threshold value to the decision circuit which determines an output signal based on the delayed signal and the calculated threshold value.

Claim 9

A circuit arrangement as claimed in claim 1, wherein the signal or the samples obtained from the matched filter are filtered in the median filter so that a median of 2k+1 samples is calculated, where k is an integer, and wherein the output of the median filter is input to a calculation circuit, which calculates an output signal.

Claim 10

A circuit for receiving a signal that includes a spreading code, comprising: matched filter means having an input for receiving the signal and an output, said matched filter means having a filter characteristic that is matched to the spreading code; delay means having an input coupled to said output of said matched filter means for delaying a signal output from said matched filter means by k samples, where k is an integer, said delay means having an output; median filter means having an input coupled to said output of said matched filter means and an output, said median filter means processing said output of said matched filter means and determining a median thereof for each of 2k+1 samples of said output of said matched filter means; and further circuit means coupled to said output of said delay means and to said output of said median filter means for processing said output of said delay means in accordance with said output of said median filter means.

Claim 11

A circuit for receiving a signal that includes a spreading code, comprising: matched filter means having an input for receiving the signal and an output, said matched filter means having a filter characteristic that is matched to the spreading code; delay means having an input coupled to said output of said matched filter means for delaying a signal output from said matched filter means by k samples, where k is an integer, said delay means having an output; median filter means having an input coupled to said output of said matched filter means and an output, said median filter means processing said output of said matched filter means and determining a median thereof for each of 2k+1 samples of said output of said matched filter means; and further circuit means coupled to said output of said delay means and to said output of said median filter means for processing said output of said delay means in accordance with said output of said median filter means.

Claim 12

A circuit as set forth in claim 9 wherein said further circuit means is comprised of: first circuit means, having a first input coupled to said output of said delay means and a second input coupled to said output of said median filter means, for subtracting said output of said median filter means from said output of said delay means, said first means having an output; and second circuit means, having an input coupled to said output of said first circuit means, for comparing a signal output from said first means to a reference signal, said signal output from said first means being substantially free of interference that may be present in said received signal.

Claim 13

A circuit as set forth in claim 9 wherein said further circuit means is comprised of: first circuit means, having a first input coupled to said output of said output of said median filter means, for calculating a magnitude of a threshold signal from said output of said median filter means, said first means having an output; and second circuit means, having a first input coupled to said output of said delay means and a second input coupled to said output of said first circuit means, for comparing a signal output from said first delay means to said threshold signal.

Claim 14

A circuit for receiving a signal that includes a spreading code, comprising: matched filter means having an input for receiving the signal and an output, said matched filter means having a filter characteristic that is matched to the spreading code; median filter means having an input coupled to said output of said matched filter means and an output, said median filter means processing said output of said matched filter means and determining a median thereof for each of 2k+1 samples of said output of said matched filter means, where k is an integer; and further circuit means coupled to said output of said median filter means for processing said output of said median filter means to estimate an interference level present in said received signal.

Claim 15

A circuit for receiving a signal that includes a spreading code, comprising: matched filter means having an input for receiving the signal and an output, said matched filter means having a filter characteristic that is matched to the spreading code; median filter means having an input coupled to said output of said matched filter means and an output, said median filter means processing said output of said matched filter means and determining a median thereof for each of 2k+1 samples of said output of said matched filter means, where k is an integer; and further circuit means coupled to said output of said median filter means for processing said output of said median filter means to estimate an interference level present in said received signal.