Spread spectrum signal detector

Claim 2

A spread spectrum signal detector comprising: means for receiving a spread spectrum signal; means, coupled to said receiving means, for sampling in sequence a modulated carrier of said received signal in order to generate in-phase (I) and quadrature-phase (Q) samples of said modulated carrier in accordance with threshold signals; means, coupled to the outputs of said sampling means, for aligning in time each sequential pair of said in-phase (I) and quadrature-phase (Q) samples of said modulated carrier; means, coupled to said outputs of said I and 0 samples aligning means, for generating said threshold signals for coupling to said sampling means; and means, coupled to said outputs of said I and Q samples aligning means, for generating an automatic gain control (AGC) signal for coupling to said receiving means.

Claim 3

The spread spectrum signal detector as recited in Claim 1 wherein said threshold signals comprise a zero-mean threshold signal level (TO) and offset threshold signal levels TO + 01 and TO-D2 above and below, respectively, said zero-mean threshold signal level.

Claim 4

The spread spectrum signal detector as recited in Claim 2 wherein said receiving means comprises means for receiving said AGC signal for setting a fixed percentage of threshold crossings outside said offset threshold signal levels.

Claim 5

The spread spectrum signal detector as recited in Claim 1 wherein said sampling means provides a sign bit and a magnitude bit measurement for each sample of said I and Q.

Claim 6

The spread spectrum signal detector as recited in Claim 1 wherein said threshold signals generating means, is coupled to sign bit outputs of said I and Q samples provided by said aligning means for generating said threshold signals.

Claim 7

The spread spectrum signal detector as recited in Claim 1 wherein said AGC generating means is coupled to sign and magnitude bit outputs of said I and Q samples provided by said aligning means for generating said AGC signal.

Claim 8

The spread spectrum signal detector as recited in Claim 1 wherein said sampling means comprises: first comparator means for detecting phase reversals of said received signal; and second comparator means for detecting the magnitude of said received signal above predetermined outside threshold levels.

Claim 9

The spread spectrum signal detector as recited in Claim 1 wherein said sampling means comprises a zero-crossing detection means for performing said sampling of said modulated carrier.

Claim 10

The spread spectrum signal detector as recited in Claim 1 wherein said sampling means comprises: means for comparing said sampled modulated carrier signal to threshold signaLlevels, a first one of said threshold signal levels (TO) set for detecting zero-crossings of said sampled signal, a second one of said threshold levels (TO + D1 ) set for a positive increment above T0, and a third one of said threshold levels (TO-D2) set for a negative increment below T0; and means coupled to said comparing means for storing a sign and magnitude measurement of said sampled signal, said magnitude being stored in a first register if said magnitude is positive or stored in a second register if said magnitude is negative, the selection of said first or second register being made in accordance with said stored sign measurement.

Claim 11

The spread spectrum signal detector as recited in Claim 1 wherein said detector further comprises a demodulator means coupled to said I and Q samples outputs of said I and Q samples aligning means for converting said samples to baseband demodulated samples.

Claim 12

The spread spectrum signal detector as recited in Claim 10 wherein said demodulator means comprises means for inverting sign and magnitude bits on every other pair of said I and Q samples.

Claim 13

The spread spectrum signal detector as recited in Claim 2 wherein said AGC signal generating means comprises: statistical accumulator means for setting a level of said AGC signal based on the number of times a peak amplitude of said modulated carrier of said received signal exceeds said offset threshold signals TO + D1 and TO-D2; means coupled to a digital output of said statistical accumulator means for converting said digital output to an analog signal; and low pass filter means coupled to said digital to analog converting means output for coupling said AGC signal to said receiving means.

Claim 14

The spread spectrum signal detector as recited in Claim 12 wherein said statistical accumulator comprises: means for generating an internal crossings signal (ICS) indicating when said ICN signal is a logic 0 that said I and Q samples are both inside the offset threshold levels TO + D1 and TO-D2 and when said ICN signal is a logic 1 that either said I or Q sample is outside said offset threshold levels; means coupled to said ICN signal generating means for selecting a predetermined weighting factor in accordance with the logic state of said ICN signal; and means coupled to said weighting factor selecting means for adding a plurality of sequential weighting factors for nulling the accumulated sum in said adding means which provides a digital representation of said AGC level in accordance with a predetermined percentage of outside threshold crossings.

Claim 15

The spread spectrum signal detector as recited in Claim 13 wherein said adding means of said statistical accumulator further comprises: means for providing a digital word to an input of said adding means; and means coupled to said adding means for determining a correct adding means output when overflow and underflow occurs using a sign bit of said digital word and an extra bit of said adding means to select said adding means output.

Claim 16

A spread spectrum signal detector comprising: means for receiving a spread spectrum signal; means, coupled to said receiving means, for sampling in sequence a modulated carrier of said received signal in order to generate in-phase (I) and quadrature-phase (Q) samples of said modulated carrier in accordance with threshold signals; means, coupled to the outputs of said sampling means, for aligning in time each sequential pair of said in- .phase (I) and quadrature-phase (Q) samples of said modulated carrier; means, coupled to outputs of said I and Q samples aligning means, for generating said threshold signals for coupling to said sampling means; means, coupled to said outputs of said I and Q samples aligning means, for generating an automatic gain control (AGC) signal for coupling to said receiving means; means, coupled to said I and Q samples outputs of said aligning means, for converting said samples to baseband demodulated samples; and means, coupled to the I and Q baseband demodulated sample outputs of said converting means, for performing spread spectrum signal processing, said I and Q baseband signals being aligned in time for said processing in accordance with an I and Q reference aligner means.

Claim 17

A spread spectrum signal detector comprising: means for receiving a spread spectrum signal; means, coupled to said receiving means, for sampling in sequence a modulated carrier of said received signal in order to generate in-phase (I) and quadrature-phase (Q) samples of said modulated carrier in accordance with threshold signals; means, coupled to the outputs of said sampling means, for aligning in time each sequential pair of said in- .phase (I) and quadrature-phase (Q) samples of said modulated carrier; means, coupled to outputs of said I and Q samples aligning means, for generating said threshold signals for coupling to said sampling means; means, coupled to said outputs of said I and Q samples aligning means, for generating an automatic gain control (AGC) signal for coupling to said receiving means; means, coupled to said I and Q samples outputs of said aligning means, for converting said samples to baseband demodulated samples; and means, coupled to the I and Q baseband demodulated sample outputs of said converting means, for performing spread spectrum signal processing, said I and Q baseband signals being aligned in time for said processing in accordance with an I and Q reference aligner means.

Claim 18

The spread spectrum signal detector as recited in Claim 15 wherein said threshold signals comprise a zero-mean threshold signal level (TO) and offset threshold signal levels TO + D1 and TO-D2 above and below, respectively, said zero-mean threshold signal level.

Claim 19

The spread spectrum signal detector as recited in Claim 16 wherein said receiving means comprises means for receiving said AGC signal for setting a fixed percentage of threshold crossings outside said offset threshold signal levels.

Claim 20

The spread spectrum signal detector as recited in Claim 15 wherein said sampling means provides a sign bit and magnitude bit measurement for each sample of said I and Q.

Claim 21

The spread spectrum signal detector as recited in Claim 15 wherein said threshold signals generating means is coupled to sign bit outputs of said I and Q samples provided by said aligning means for generating said threshold signals.

Claim 22

The spread spectrum signal detector as recited in Claim 15 wherein said AGC generating means is coupled to sign and magnitude bit outputs of said I and Q samples provided by said aligning means for generating said AGC signal.

Claim 23

The spread spectrum signal detector as recited in Claim 15 wherein said sampling means comprises: first comparator means for detecting phase reversals of said received signal; and second comparator means for detecting the magnitude of said received signal above predetermined thresholds.

Claim 24

The spread spectrum signal detector as recited in Claim 15 wherein said sampling means comprises a zero-crossing detection means for performing said sampling of said modulated carrier.

Claim 25

The spread spectrum signal detector as recited in Claim 15 wherein said sampling means comprises: means for comparing said sampled modulated carrier signal to threshold signal levels, a first one of said threshold signal levels (TO) set for detecting zero-crossings of said sampled signal, a second one of said threshold levels (TO + D1) set for a positive increment above T0, and a third one of said threshold levels (T0-D2) set for a negative increment below T0; and means coupled to said comparing means for storing a sign and magnitude measurement of said sampled signal, said magnitude being stored in a first register if said magnitude is positive or stored in a second register if said magnitude is negative, the selection of said first or second register being made in accordance with said stored sign measurement.

Claim 26

The spread spectrum detector as recited in Claim 15 wherein said baseband demodulator converter means converts said samples to baseband demodulated samples by inverting sign and magnitude bits on every other pair of said I and Q samples.

Claim 27

The spread spectrum signal detector as recited in Claim 16 wherein said AGC signal generating means comprises: statistical accumulator means for setting a level of said AGC signal based on the number of times a peak amplitude of said modulated carrier of said received signal exceeds said offset thresholds signals TO + D1 and TO-D2; means, coupled to a digital output of said statistical accumulator means, for converting said digital output to an analog signal; and low pass filter means, coupled to said digital to analog converting means output, for coupling said AGC signal to said receiving means.

Claim 28

The spread spectrum signal detector as recited in Claim 16 wherein said statistical accumulator comprises: means for generating an internal crossings signal (ICS) indicating when said ICN signal is a logic 0 that said I and Q samples are both inside the offset threshold levels TO+D1 and TO-D2 and when said ICN signal is a logic 1 that either said I or Q sample is outside said offset threshold levels; means coupled to said ICN signal generating means for selecting a predetermined weighting factor in accordance with the logic state of said ICN signal; and means coupled to said weighting factor selecting means for adding a plurality of sequential weighting factors for nulling the accumulated sum in said adding means which provides a digital representation of said AGC level in accordance with a predetermined percentage of outside threshold crossings.

Claim 29

The spread spectrum signal detector as recited in Claim 26 wherein said adding means of said statistical accumulator further comprises: means for providing a digital word to an input of said adding means; and means coupled to said adding means for determining a correct adding means output when overflow and underflow occurs using a sign bit of said digital word and an extra bit of said adding means to select said adding means output.

Claim 32

The method as recited in Claim 28 wherein said step of generating threshold signals comprises the steps of: generating a zero-mean threshold signal level (TO); and generating offset threshold signal levels TO + D1 and TO-D2 above and below, respectively, said zero mean threshold signal level.

Claim 33

The method as recited in Claim 28 wherein said step of sampling a modulated carrier of said received signal comprises the steps of: comparing said sampled modulated carrier signal to said threshold signal levels, a first one of said threshold signal levels (TO) set for detecting zero-crossings of said sampled signal, a second one of said threshold levels (TO+D1) set for a positive increment above T0, and a third one of said threshold levels (TO-D2) set for a negative increment below T0; and storing a sign and magnitude measurement of said sampled signal, said magnitude being stored in a first register if said magnitude is positive or stored in a second register if said magnitude is negative, the selection of said first or second register being made in accordance with said stored sign measurement.

Claim 34

A spread spectrum receiver comprising: means for controlling the gain of an input signal in accordance with an AGC signal; means, coupled to the output of said controlling means, for sampling said input signal to obtain a plurality of sequential in-phase (I) and quadrature-phase (Q) samples in accordance with a first sampling clock frequency and predetermined threshold signals; means, coupled to the output of said sampling means, for aligning in time said in-phase (I) and quadrature-phase (Q) samples in accordance with a second sampling clock frequency; means, coupled to the outputs of said aligning means, for generating said AGC signal; and means, coupled to I and Q sign outputs of said aligning means, for generating said threshold signals coupled to said sampling means.

Claim 35

A spread spectrum receiver comprising: means for controlling the gain of an input signal in accordance with an AGC signal; means, coupled to the output of said controlling means, for sampling said input signal to obtain a plurality of sequential in-phase (I) and quadrature-phase (Q) samples in accordance with a first sampling clock frequency and predetermined threshold signals; means, coupled to the output of said sampling means, for aligning in time said in-phase (I) and quadrature-phase (Q) samples in accordance with a second sampling clock frequency; means, coupled to the outputs of said aligning means, for generating said AGC signal; and means, coupled to I and Q sign outputs of said aligning means, for generating said threshold signals coupled to said sampling means.

Claim 36

The receiver as recited in Claim 28 wherein said receiver comprises means coupled to the outputs of said I and Q aligning means for converting said outputs to baseband demodulated signals.

Claim 37

The receiver as recited in Claim 28 wherein said threshold signals comprise a zero means threshold signal (TO) and offset threshold signals TO + D1 and TO-D2 above and below, respectively, said zero means signal level.

Claim 38

A zero-crossing detector for sampling in. sequence in-phase (I) and quadrature (Q) components of an input signal comprising: means for comparing a sampled signal to threshold signal levels, a first one of said threshold signal levels (TO) set for detecting zero-crossings of said sampled signal, a second one of said threshold levels (TO + D1 ) set for a positive increment above T0, and a third one of said threshold levels (T0-D2) set for a negative increment below T0; and means coupled to said comparing means for storing a sign and magnitude measurement of said sampled signal, said magnitude being stored in a first register if said magnitude is positive or stored in a second register if said magnitude is negative, the selection of said first or second register being made in accordance with said stored sign measurement.

Claim 39

A zero-crossing detector for sampling in. sequence in-phase (I) and quadrature (Q) components of an input signal comprising: means for comparing a sampled signal to threshold signal levels, a first one of said threshold signal levels (TO) set for detecting zero-crossings of said sampled signal, a second one of said threshold levels (TO + D1 ) set for a positive increment above T0, and a third one of said threshold levels (T0-D2) set for a negative increment below T0; and means coupled to said comparing means for storing a sign and magnitude measurement of said sampled signal, said magnitude being stored in a first register if said magnitude is positive or stored in a second register if said magnitude is negative, the selection of said first or second register being made in accordance with said stored sign measurement.

Claim 40

An accumulator of a spread spectrum signal detector comprising: means for providing a first digital word; means coupled to said digital word providing means for adding said first digital word to a second digital word; and means coupled to said adding means for determining a sum when overflow and underflow occurs in said adding means using a sign bit of said first digital word and an extra bit output of said adding means to select said sum.

Claim 41

An accumulator of a spread spectrum signal detector comprising: means for providing a first digital word; means coupled to said digital word providing means for adding said first digital word to a second digital word; and means coupled to said adding means for determining a sum when overflow and underflow occurs in said adding means using a sign bit of said first digital word and an extra bit output of said adding means to select said sum.

Claim 42

A threshold level generator for a spread spectrum signal detector comprising: first register means for storing a sign bit sample of an in-phase (I) component of a carrier signal; first up/down counter means coupled to said first register means for counting up or down based on the sign bit stored in said first register means; second register means coupled to an output of said first register means for storing said I sign bit one-half clock period later for underflow and overflow control of said first up/down counter means; a set output of said second register is coupled to two least significant stages of said first up/down counter means and a reset output of said second register is coupled to ten most significant stages of said first up/down counter means for preloading down said first up/down counter on overflow and preloading up said first up/down counter means on underflow; third register means coupled to the output of said first up/down counter means for storing an output of said first up/down counter means; fourth register means for storing a sign bit sample of a quadrature-phase (Q) component of said carrier signal; second up/down counter means coupled to said fourth register means for counting up or down based on the sign bit stored in said first register means; fifth register means coupled to an output of said fourth register means for storing said Q sign bit one-half clock period later for underflow and overflow control of said second up/down counter means; a set output of said fifth register is coupled to two least significant stages of said second up/down counter means and a reset output of said fifth register is coupled to ten most significant stages of said second up/down counter means for preloading down said second up/down counter means on overflow and preloading up said second counter means on underflow; sixth register means coupled to the output of said second up/down counter means for storing an output of said second up/down counter means; adder means coupled to the outputs of said third register means and said sixth register means for determining the sum of the outputs of said first up/down counter means and said second up/down counter means, said sum determining a zero-mean threshold level.

Claim 43

A threshold level generator for a spread spectrum signal detector comprising: first register means for storing a sign bit sample of an in-phase (I) component of a carrier signal; first up/down counter means coupled to said first register means for counting up or down based on the sign bit stored in said first register means; second register means coupled to an output of said first register means for storing said I sign bit one-half clock period later for underflow and overflow control of said first up/down counter means; a set output of said second register is coupled to two least significant stages of said first up/down counter means and a reset output of said second register is coupled to ten most significant stages of said first up/down counter means for preloading down said first up/down counter on overflow and preloading up said first up/down counter means on underflow; third register means coupled to the output of said first up/down counter means for storing an output of said first up/down counter means; fourth register means for storing a sign bit sample of a quadrature-phase (Q) component of said carrier signal; second up/down counter means coupled to said fourth register means for counting up or down based on the sign bit stored in said first register means; fifth register means coupled to an output of said fourth register means for storing said Q sign bit one-half clock period later for underflow and overflow control of said second up/down counter means; a set output of said fifth register is coupled to two least significant stages of said second up/down counter means and a reset output of said fifth register is coupled to ten most significant stages of said second up/down counter means for preloading down said second up/down counter means on overflow and preloading up said second counter means on underflow; sixth register means coupled to the output of said second up/down counter means for storing an output of said second up/down counter means; adder means coupled to the outputs of said third register means and said sixth register means for determining the sum of the outputs of said first up/down counter means and said second up/down counter means, said sum determining a zero-mean threshold level.