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Patent US5426591A successfully refreshed from Google Patents.
US5426591A
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Apparatus and method for improving the timing performance of a circuit
Assignee: Philips Semiconductors Inc
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Filing: 1994-01-28
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Granted: 1995-06-20
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Expires: 2014-01-28
Abstract
Abstract A computer aided design system and method for automatically modifying a specified Hardware Description Language (HDL) characterization of a circuit to reduce signal delays on critical paths of the circuit is described. The specified circuit is analyzed with a logic synthesizer including a novel cell-based timing verifier that determines if a circuit meets specified timing requirements. Timing requirements are tested by computing a slack value for each node of the circuit at the component (macrocell) level, where the slack value represents the difference between the required arrival time of a signal at each circuit node and the computed worst case signal arrival time for the node. The output node having the most negative slack value is identified as a critical node. The HDL description of the circuit corresponding to the critical node is modified with a synthesis directive to substitute the original datapath cell with a better cell in order to improve the circuit's timing performance. The revised HDL description of the circuit is then re-synthesized. Improvements to the circuit may be repeated in this fashion until the circuit meets all timing constraints.
Inventors
- 👤 Arnold Ginetti
- 👤 Mossaddeq Mahmood
- 👤 Balmukund Sharma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:50
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/3312; G06F2119/00; G06F2119/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
96 words
An apparatus for designing a circuit, said apparatus comprising: a Hardware Description Language Register-Transfer Level synthesizer for synthesizing a hardware description language characterization of a circuit into an instance-level circuit including a plurality of interconnected multiple gate components; a cell-based timing verifier to test the timing performance of said instance-level circuit, said cell-based timing verifier relying upon an instance level timing analysis of said instance-level circuit; and means for replacing at least one of said plurality of interconnected multiple gate components with a new multiple gate component to improve the timing performance of said instance-level circuit.
Claim 2
Independent Claim
96 words
An apparatus for designing a circuit, said apparatus comprising: a Hardware Description Language Register-Transfer Level synthesizer for synthesizing a hardware description language characterization of a circuit into an instance-level circuit including a plurality of interconnected multiple gate components; a cell-based timing verifier to test the timing performance of said instance-level circuit, said cell-based timing verifier relying upon an instance level timing analysis of said instance-level circuit; and means for replacing at least one of said plurality of interconnected multiple gate components with a new multiple gate component to improve the timing performance of said instance-level circuit.
Claim 3
Dependent Claim
28 words
The apparatus of claim 1 wherein said cell-based timing verifier utilizes accumulated real wiring capacitance values of primitive cells to test the timing performance of said instance-level circuit.
Claim 4
Dependent Claim
45 words
The apparatus of claim 2 wherein said cell-based timing verifier includes: means for propagating signal arrival times at each of said plurality of interconnected multiple gate components; and means for back-propagating required signal arrival times at each of said plurality of interconnected multiple gate components.
Claim 5
Dependent Claim
61 words
The apparatus of claim 1 wherein said cell-based timing verifier generates a set of cell timing values, said cell timing values including a plurality of slack values, each of said slack values representing the difference between a required arrival time of a signal and a computed worst case signal arrival time for one of said plurality of interconnected multiple gate components.
Claim 6
Dependent Claim
20 words
The apparatus of claim 4 wherein said replacing means selects said new multiple gate component based upon said slack values.
Claim 7
Dependent Claim
30 words
The apparatus of claim 1 wherein said Register-Transfer Level synthesizer generates a synthesis report describing circuit components utilized in said instance-level circuit and summarizing physical characteristics of said instance-level circuit.
Claim 8
Independent Claim
90 words
A method of designing a circuit, said method comprising the steps of: synthesizing a hardware description language characterization of a circuit into an instance-level circuit including a plurality of interconnected multiple gate components; executing an instance level timing analysis of said instance-level circuit to generate a set of cell time values; and replacing at least one of said plurality of interconnected multiple gate components with a new multiple gate component to improve the timing performance of said instance-level circuit, said replacing step relying upon said set of cell timing values.
Claim 9
Independent Claim
90 words
A method of designing a circuit, said method comprising the steps of: synthesizing a hardware description language characterization of a circuit into an instance-level circuit including a plurality of interconnected multiple gate components; executing an instance level timing analysis of said instance-level circuit to generate a set of cell time values; and replacing at least one of said plurality of interconnected multiple gate components with a new multiple gate component to improve the timing performance of said instance-level circuit, said replacing step relying upon said set of cell timing values.
Claim 10
Dependent Claim
43 words
The method of claim 7 wherein said executing step includes the steps of: propagating signal arrival times at each of said plurality of interconnected multiple gate components; and back-propagating required signal arrival times at each of said plurality of interconnected multiple gate components.
Claim 11
Dependent Claim
20 words
The method of claim 7 wherein said executing step results in the generation of a set of cell timing values.
Claim 12
Dependent Claim
40 words
The method of claim 7 wherein said replacing step includes the step of placing a directive in said hardware description language characterization of said circuit, said directive specifying a multiple gate component to execute a specified hardware description language operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |