Array of non-volatile sonos memory cells

Claim 2

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; a word line commonly interconnecting the adjacent SONOS gates of the pair; separate bit lines separately electrically engaging the separated diffusion regions of the pair; and further comprising LDD regions for each of the adjacent gates, the LDD regions being angled from the source/drain diffusion regions; and a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions.

Claim 3

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; a word line commonly interconnecting the adjacent SONOS gates of the pair; separate bit lines separately electrically engaging the separated diffusion regions of the pair; and further comprising LDD regions for each of the adjacent gates, the LDD regions being angled from the source/drain diffusion regions; a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions; and an isolation region at the trench base between the source/drain diffusion regions, the isolation region comprising a conductivity enhancing impurity of the second type.

Claim 4

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; a word line commonly interconnecting the adjacent SONOS gates of the pair; separate bit lines separately electrically engaging the separated diffusion regions of the pair; and further comprising LDD regions for each of the adjacent gates, the LDD regions being angled from the source/drain diffusion regions; a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions; and an isolation region at the trench base between the source/drain diffusion regions, the isolation region comprising a conductivity enhancing impurity of the second type.

Claim 5

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; a word line commonly interconnecting the adjacent SONOS gates of the pair; separate bit lines separately electrically engaging the separated diffusion regions of the pair; wherein the separated source/drain diffusion regions are each downwardly elongated; and further comprising: LDD regions for each of the adjacent gates, the LDD regions being angled from the downwardly elongated source/drain diffusion regions; and a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions.

Claim 6

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; a word line commonly interconnecting the adjacent SONOS gates of the pair; separate bit lines separately electrically engaging the separated diffusion regions of the pair; wherein the separated source/drain diffusion regions are each downwardly elongated; and further comprising: LDD regions for each of the adjacent gates, the LDD regions being angled from the downwardly elongated source/drain diffusion regions; and a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions.

Claim 7

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; a word line commonly interconnecting the adjacent SONOS gates of the pair; separate bit lines separately electrically engaging the separated diffusion regions of the pair; wherein the separated source/drain diffusion regions are each downwardly elongated; and further comprising: LDD regions for each of the adjacent gates, the LDD regions being angled from the downwardly elongated source/drain diffusion regions; a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions; and an isolation region at the trench base between the source/drain diffusion regions, the isolation region comprising a conductivity enhancing impurity of the second type.

Claim 8

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; a word line commonly interconnecting the adjacent SONOS gates of the pair; separate bit lines separately electrically engaging the separated diffusion regions of the pair; wherein the separated source/drain diffusion regions are each downwardly elongated; and further comprising: LDD regions for each of the adjacent gates, the LDD regions being angled from the downwardly elongated source/drain diffusion regions; a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions; and an isolation region at the trench base between the source/drain diffusion regions, the isolation region comprising a conductivity enhancing impurity of the second type.

Claim 9

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define downwardly elongated and separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; LDD regions for each of the adjacent gates, the LDD regions being angled from the downwardly elongated source/drain diffusion regions; a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions; an isolation region at the trench base between the source/drain diffusion regions, the isolation region comprising a conductivity enhancing impurity of the second type; a word line commonly interconnecting the adjacent SONOS gates of the pair; and separate bit lines separately electrically engaging the separated diffusion regions of the pair at locations peripheral of the array area.

Claim 10

An array of SONOS memory cells; the array including non-volatile, single gate SONOS memory cell transistors having electrically isolated adjacent source/drain regions; the array comprising: a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define downwardly elongated and separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; LDD regions for each of the adjacent gates, the LDD regions being angled from the downwardly elongated source/drain diffusion regions; a source/drain interconnecting region between each of the separated source/drain diffusion regions and its respective gate, the source/drain interconnecting regions being angled from the source/drain diffusion regions; an isolation region at the trench base between the source/drain diffusion regions, the isolation region comprising a conductivity enhancing impurity of the second type; a word line commonly interconnecting the adjacent SONOS gates of the pair; and separate bit lines separately electrically engaging the separated diffusion regions of the pair at locations peripheral of the array area.