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US5424248A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making an integrated circuit with variable pad pitch

Assignee: Philips Semiconductors Inc
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Filing: 1993-10-25
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Granted: 1995-06-13
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Expires: 2013-10-25
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Abstract

Abstract A method for making an integrated circuit characterized by: determining a range of bonding pad pitches which varies between a minimum bonding pad pitch and a maximum bonding pad pitch; setting a driver pitch to the minimum bonding pad pitch; forming a base set including a plurality of drivers having the determined driver pitch; forming customization layers over the base set, where the customization layers include a plurality of bonding pads having a pad pitch greater than the minimum bonding pad pitch but less than or equal to the maximum bonding pad pitch; and coupling some, but not all, of the drivers to the pads. As a result, a single base set can be used to make integrated circuits having a range of bonding pad pitches. The method and structure of the present invention are very well adapted for use in gate array integrated circuits.

Inventors

  • 👤 Bryan C. Doi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 20:28
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/49; H10D; H10D84/00; H10D84/90; H10D84/998

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 181 words
A method for making a plurality of gate array integrated circuits comprising: determining a range of bonding pad pitches varying between a minimum bonding pad pitch and a maximum bonding pad pitch; setting a driver pitch to said minimum bonding pad pitch; forming a plurality of base means comprising a base set of layers, wherein each of said base means includes a plurality of drivers having said driver pitch; selecting a plurality of said base means for customization; forming a customization means comprising metal connect layers over each of said selected plurality of base means, wherein each of said customization means comprises an insulating layer provided with conductive via means and a plurality of bonding pads having a pad pitch greater than said minimum bonding pad pitch but less than or equal to said maximum bonding pad pitch, wherein said pad pitch of said bonding pads is different on at least two of said customization means; and coupling some, but not all, of said drivers of each base means to said pads of a customization means, using said conductive via means.
Claim 2
Independent Claim 181 words
A method for making a plurality of gate array integrated circuits comprising: determining a range of bonding pad pitches varying between a minimum bonding pad pitch and a maximum bonding pad pitch; setting a driver pitch to said minimum bonding pad pitch; forming a plurality of base means comprising a base set of layers, wherein each of said base means includes a plurality of drivers having said driver pitch; selecting a plurality of said base means for customization; forming a customization means comprising metal connect layers over each of said selected plurality of base means, wherein each of said customization means comprises an insulating layer provided with conductive via means and a plurality of bonding pads having a pad pitch greater than said minimum bonding pad pitch but less than or equal to said maximum bonding pad pitch, wherein said pad pitch of said bonding pads is different on at least two of said customization means; and coupling some, but not all, of said drivers of each base means to said pads of a customization means, using said conductive via means.
Claim 3
Dependent Claim 31 words
A method as recited in claim 1 wherein said minimum bonding pad pitch is 4 mils, said maximum bonding pad pitch is 5 mils, and said driver pitch is 4 mils.
Claim 4
Dependent Claim 28 words
A method as recited in claim 1 wherein said pad pitch is at least 5% greater than said driver pitch, but no greater than said maximum pad pitch.
Claim 5
Dependent Claim 30 words
A method as recited in claim 1 wherein said pad pitch is between about 5% and 95% greater than said driver pitch, but no greater than said maximum pad pitch.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-06-12 1998-12-12 1999-06-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-06-12 2002-12-12 2003-06-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-06-12 2006-12-12 2007-06-13 $7700.00 Window Closed / Lapsed

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