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EP0306620A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Bus structure for integrated circuit chip

Assignee: Fairchild Semiconductor Corp
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Filing: 1984-09-07
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Granted: —
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Expires: 2004-09-07
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Abstract

Abstract An integrated circuit chip comprising plural gates (12) connected in parallel to a power supply network (V+) by a first bus (14) which extends from a bonding pad (18) and which is disposed adjacent said gates, and a second bus (16) having a portion disposed parallel to and adjacent said portion of said first bus, wherein - in order to control the voltage drop along ground and power buses - at least a portion of said first bus lying adjacent said gates has a width which decreases with increasing distance from said bonding pad in proportion to the magnitude of the current conducted in the bus; said portion of said second bus has a width which increases in a manner complementary to the width of said portion of said first bus and in proportion to the magnitude of current conducted in said second bus; and said gates are connected in parallel to each of said first and second buses.

Inventors

  • 👤 James M. Early

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 20:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10B; H10B20/00

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 147 words
An integrated circuit chip comprising plural gates (12) connected in parallel to a power supply network (V+) by a first bus (14) which extends from a bonding pad (18) and which is disposed adjacent said gates, and a second bus (16) having a portion disposed parallel to and adjacent said portion of said first bus, characterized in that at least a portion of said first bus lying adjacent said gates has a width which decreases with increasing distance from said bonding pad in proportion to the magnitude of the current conducted in the bus; said portion of said second bus has a width which increases in a manner complementary to the width of said portion of said first bus and in proportion to the magnitude of current conducted in said second bus; and said gates are connected in parallel to each of said first and second buses.
Claim 2
Dependent Claim 147 words
An integrated circuit chip comprising plural gates (12) connected in parallel to a power supply network (V+) by a first bus (14) which extends from a bonding pad (18) and which is disposed adjacent said gates, and a second bus (16) having a portion disposed parallel to and adjacent said portion of said first bus, characterized in that at least a portion of said first bus lying adjacent said gates has a width which decreases with increasing distance from said bonding pad in proportion to the magnitude of the current conducted in the bus; said portion of said second bus has a width which increases in a manner complementary to the width of said portion of said first bus and in proportion to the magnitude of current conducted in said second bus; and said gates are connected in parallel to each of said first and second buses.
Claim 3
Dependent Claim 58 words
The integrated circuit chip of claim 1 characterized in that, in addition to said parallel and adjacent portion called first portion, said second bus has a second portion which connects an end of said first portion that is remote from said edge with a second bonding pad (20) located at said one edge adjacent said first bonding pad.
Claim 4
Dependent Claim 51 words
The integrated circuit chip of claim 2 characterized in that said second portion of said second bus is disposed on a different layer of said chip than said first bus and said first portion of said second bus, and overlies said first bus and said first portion of said second bus.
Claim 5
Dependent Claim 53 words
The integrated circuit chip of claim 1 or 2 wherein said portion of said first bus and said first portion of said second bus have stepped widths and said connecting means comprise conductors that respec­tively connect each gate to the buses at a location adjacent each step in the width of the bus.
Claim 6
Dependent Claim 39 words
The integrated circuit chip of claim 4 wherein all of the conductors connecting the gates to the first bus have the same length and all of the conductors connecting the gates to the second bus have the same length.
Claim 7
Dependent Claim 33 words
The integrated circuit chip of claim 4 wherein the total length of the pair of conductors which respectively connect a gate to said first and second buses is the same for each gate.
Claim 8
Dependent Claim 24 words
The integrated circuit chip of claim 2 wherein said first and second bonding pads are successive pads along said one edge of the chip.

References Cited (Backward Citations)

EP0074825A2 Cited

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