Master slice integrated circuit having a reduced chip size and a reduced power supply noise

Claim 1

A master slice integrated circuit including: an internal cell zone which is defined at a center area of an integrated circuit chip and in which a number of internal cells are located in the form of a matrix; an input/output cell zone defined on said integrated circuit chip so as to surround said internal cell zone, said input/output cell zone including therein a number of input/output cells located in a single array along a side of said integrated circuit chip; a number of signal pads and a number of power supply pads located in a row at an outside of said input/output cell zone and along a peripheral edge region of said integrated circuit chip, each of said input/output cells being connected to a corresponding one of said signal pads; and at least one power supply wiring conductor located to pass over all said input/output cells and therefore to surround said internal cell zone, said at least one power supply wiring conductor being connected to said power supply pads, each power supply pad being disposed in-line with a boundary line between each pair of adjacent signal input/output pads, and two signal pads being disposed between each pair of consecutive power pads along a peripheral edge of said integrated circuit chip.