Method of making an EPROM cell with a readily scalable interpoly dielectric

Claim 2

A process for fabricating a nonvolatile programmable, read only memory comprising a plurality of memory cells each having a floating gate of polysilicon electrically isolated from a superimposed control gate by a dielectric layer, comprising the steps of: treating the surface of a patterned layer of polysilicon constituting said floating gates at a temperature between 900° C. and 1100° C. for between 15 and 150 seconds in a nitrogen atmosphere to form a nitridized surface layer of polysilicon; depositing a layer of silicon nitride over said nitridized surface layer; oxidizing part of the thickness of said deposited layer of silicon nitride in the presence of water vapor at a temperature comprised between 900° C. and 1000° C. for a time sufficient to grow a dielectric layer of silicon oxide having a thickness comprised between 5 and 20 nm; and depositing and patterning a control gate over said floating gates, said dielectric layer of silicon oxide isolating the floating gate of each cell from a control gate.

Claim 3

The process of claim 1, wherein said step of depositing a layer of silicon nitride is performed to a thickness of about 12 nm.

Claim 4

The process of claim 1, wherein said step of depositing a layer of silicon nitride is performed at about 780° C.

Claim 5

The process of claim 1, wherein said step of depositing a layer of silicon nitride is performed from a mixture comprising ammonia and dichlorosilane.

Claim 6

The process of claim 1, wherein said oxide layer is grown to a thickness of about 10 nm.

Claim 7

The process of claim 1, wherein said nitridized layer, said layer of silicon nitride, and said layer of silicon oxide have a total real thickness in the range of 10-30 nm.

Claim 8

The process of claim 1, wherein said oxidizing step is performed in an atmosphere of steam and oxygen.

Claim 9

The process of claim 1, wherein said oxidizing step is performed at a temperature of about 950° C.

Claim 10

The process of claim 1, wherein said oxidizing step is performed for more than one hour.

Claim 11

A process for fabricating a nonvolatile memory, comprising the steps of: providing a substrate having active device locations therein; depositing an insulated polysilicon layer, and patterning said insulated polysilicon layer to form isolated floating gates over plural ones of said active device locations; treating the surface of said insulated polysilicon layer, at a temperature in the range of 900° C.-1100° C. for between 15 and 150 seconds in a nitrogen atmosphere, to form a nitridized surface layer thereon; depositing a layer of silicon nitride over said nitridized surface layer; oxidizing part of the thickness of said deposited layer of silicon nitride, in the presence of water vapor, at a temperature in the range of 900° C.-1000° C., for a time sufficient to grow a dielectric layer of silicon oxide having a thickness comprised between 5 and 20 nm; and depositing a second thin film conductor layer, and patterning said second thin film conductor layer to form control gates over said floating gates, said control gates being connected to form operative transistor gates.

Claim 12

A process for fabricating a nonvolatile memory, comprising the steps of: providing a substrate having active device locations therein; depositing an insulated polysilicon layer, and patterning said insulated polysilicon layer to form isolated floating gates over plural ones of said active device locations; treating the surface of said insulated polysilicon layer, at a temperature in the range of 900° C.-1100° C. for between 15 and 150 seconds in a nitrogen atmosphere, to form a nitridized surface layer thereon; depositing a layer of silicon nitride over said nitridized surface layer; oxidizing part of the thickness of said deposited layer of silicon nitride, in the presence of water vapor, at a temperature in the range of 900° C.-1000° C., for a time sufficient to grow a dielectric layer of silicon oxide having a thickness comprised between 5 and 20 nm; and depositing a second thin film conductor layer, and patterning said second thin film conductor layer to form control gates over said floating gates, said control gates being connected to form operative transistor gates.

Claim 13

The process of claim 10, wherein said step of depositing a layer of silicon nitride is performed to a thickness of no more than 15 nm.

Claim 14

The process of claim 10, wherein said step of depositing a layer of silicon nitride is performed to a thickness of about 12 nm.

Claim 15

The process of claim 10, wherein said step of depositing a layer of silicon nitride is performed at about 780° C.

Claim 16

The process of claim 10, wherein said step of depositing a layer of silicon nitride is performed from a mixture comprising ammonia and dichlorosilane.

Claim 17

The process of claim 10, wherein said oxide layer is grown to a thickness of about 10 nm.

Claim 18

The process of claim 10, wherein said nitridized layer, said layer of silicon nitride, and said layer of silicon oxide have a total real thickness in the range of 10-30 nm.

Claim 19

The process of claim 10, wherein said oxidizing step is performed in an atmosphere of steam and oxygen.

Claim 20

The process of claim 10, wherein said oxidizing step is performed at a temperature of about 950° C.

Claim 21

The process of claim 10, wherein said oxidizing step is performed for more than one hour.