Method and apparatus for generating a pin interrupt request in a digital data processor using a dual function data direction register

Claim 1

A digital data processor, comprising: a communication bus; a plurality of integrated circuit pins, each of said plurality of integrated circuit pins having a pin logic state; a plurality of interface circuits, each of said plurality of interface circuits corresponding to a corresponding one of said plurality of integrated circuit pins, each of said plurality of interface circuits being coupled to said communication bus and being coupled to the corresponding one of said plurality of integrated circuit pins; and interrupt generation circuitry, coupled to said plurality of interface circuits; wherein each of said plurality of interface circuits comprises: a first storage means for storing a predetermined data value, said first storage means being coupled to said communication bus; a comparator for receiving an enable signal, in response to assertion of the enable signal, said comparator comparing the pin logic state of the corresponding one of said plurality of integrated circuit pins with the predetermined data value and providing a comparison result signal, said comparator being coupled to said first storage means; and a second storage means for selectively asserting the enable signal and for selectively allowing data input transfer from the corresponding one of said plurality of integrated circuit pins to said communication bus if said second storage means stores a first predetermined control value, and for selectively allowing data output transfer from said communication bus to the corresponding one of said plurality of integrated circuit pins if said second storage means stores a second predetermined control value, said second storage means being coupled to said communication bus and to said comparator; and wherein said interrupt generation circuitry comprises: a first logic circuit, said first logic circuit receiving the comparison result signal from each of said plurality of interface circuits, said first logic circuit performing one of a logical OR operation and a logical NOR operation, said first logic circuit providing a first logical result signal; a second logic circuit, said second logic circuit receiving a stop signal and a mask option signal, the mask option signal having a mask option logic state which is fixed and made unchangeable during manufacture of the digital data processor, said second logic circuit providing a second logical result signal; and a third logic circuit, said third logic circuit selectively providing an interrupt request signal in response to receiving the first and second logical result signals, said third logic circuit being coupled to said first and second logic circuits.