US5420058A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making field effect transistor with a sealed diffusion junction
Assignee: AT&T Inc
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Filing: 1993-12-01
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Granted: 1995-05-30
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Expires: 2013-12-01
Abstract
Abstract A field effect transistor is fabricated with an ion implanted silicide layer and a conducting diffusion barrier pad layer that acts as a diffusion mask. The dopants from the silicide layer are diffused into the substrate to form shallow source/drain regions.
Inventors
- 👤 Kuo-Hua Lee
- 👤 Chun-Ting Liu
- 👤 Ruichen Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:40
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
116 words
A method of making a field effect transistor on a substrate comprising the steps of: forming a gate electrode of said field effect transistor between field oxide regions, said gate electrode having an insulating top layer; depositing a first silicide layer and a conducting diffusion barrier layer, said first silicide layer and said barrier layer forming stacked landing pad layers, said layers being over said substrate and covering said gate electrode; depositing a first dielectric layer; forming a layer of resist; patterning said resist to expose portions of said dielectric layer; and removing said exposed portions of said dielectric layer to expose portions of said stacked landing pad layers, said removing forming a patterned dielectric layer.
Claim 2
Independent Claim
116 words
A method of making a field effect transistor on a substrate comprising the steps of: forming a gate electrode of said field effect transistor between field oxide regions, said gate electrode having an insulating top layer; depositing a first silicide layer and a conducting diffusion barrier layer, said first silicide layer and said barrier layer forming stacked landing pad layers, said layers being over said substrate and covering said gate electrode; depositing a first dielectric layer; forming a layer of resist; patterning said resist to expose portions of said dielectric layer; and removing said exposed portions of said dielectric layer to expose portions of said stacked landing pad layers, said removing forming a patterned dielectric layer.
Claim 3
Dependent Claim
20 words
A method as recited in claim 1 further comprising the step of: forming dielectric spacers on said patterned dielectric layer.
Claim 4
Dependent Claim
41 words
A method as recited in claim 1 comprising the further steps of depositing a second dielectric layer over said patterned landing pad and first silicide layers, and patterning said second dielectric layer to expose portions of said patterned landing pad layer.
Claim 5
Dependent Claim
19 words
A method as recited in claim 1 comprising the further step of doping said first silicide layer with dopants.
Claim 6
Dependent Claim
38 words
A method as recited in claim 4 comprising the further step of heating to cause at least some of said dopants to move from said first silicide layer to said substrate to form source/drain regions of said transistor.
Claim 7
Dependent Claim
16 words
A method as recited in claim 5 in which said dopants are n-type and p-type dopants.
Claim 8
Dependent Claim
18 words
A method as recited in claim 6 in which said n-type and p-type dopants are boron and phosphorous.
Claim 9
Dependent Claim
17 words
A method as recited in claim 1 in which said barrier layer comprises of a conducting nitride.
Claim 10
Dependent Claim
15 words
A method as recited in claim 8 in which said conducting nitride is titanium nitride.
Claim 11
Dependent Claim
28 words
A method as recited in claim 2 comprising the further step of using said patterned dielectric layer as an etch mask for etching said stacked landing pad layers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-29 | 1998-11-28 | 1999-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-29 | 2002-11-28 | 2003-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-29 | 2006-11-28 | 2007-05-30 | $7700.00 | Window Closed / Lapsed |