Generation of width modulated pulses by relatively adjusting rising and falling edges upon comparison of counter with programmably stored values

Claim 2

A pulse generating device comprising a processor and pulse generating means, said processor includes: a reference time data register for storing reference time data for defining a timing axis of a pair of pulses to be generated, first and second working time data registers for storing respectively working time data showing a time difference between both pulses of said pair of pulses to be generated and said reference time data, a calculation unit for fetching said reference time data and said working time data, and for calculating time data on a first transition for both pulses of said pair of pulses and a last transition for both pulses of said pair of pulses, and a transfer control unit for controlling transference timing of said time data for both pulses of said pair of pulses obtained in said calculation unit; said pulse generating means including: first and second pulse output registers having storage means for storing respectively status data which is a binary digit to specify the binary digit status of either pulse of said pair of pulses to be generated and having output means for outputting an output pulse, a control register for storing a calculation control signal, a transfer control signal and a reset signal, a counter for counting clock pulses, first and second time data registers for storing respectively said time data for both pulses of said pair of pulses transmitted from said transfer control unit, and first and second comparators for comparing said time data of both of said time data registers with the value of said counter so as to transmit a coincidence signal when said compared values coincide with each other; wherein said calculation unit performs a calculation defined in response to said calculation control signal stored in said control register, said transfer control unit controls said transference timing of each of said time data in response to said transfer control signal stored in said control register, said output means of said first pulse output register outputs said output pulse corresponding to a binary digit that is the same state as said status data when one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to a binary digit that is reset to the complement of said status data when a next coincidence signal is supplied, said output means of said second pulse output register outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when the next coincidence signal is supplied, said counter is reset in response to said reset signal periodically stored in said control register, and said reference time data, each of said working time data and said status data are supplied in synchronism with said reset signal from another processor.

Claim 3

A pulse generating device according to claim 1, wherein both of said pulse output registers has an inversion output terminal maintained at an inverted status of said output terminal.

Claim 4

A pulse generating device according to claim 1, wherein output switches for selecting either of said output terminals of each of said pulse output registers and said inversion output terminal are provided, and each of said switches is controlled in response to an output switch control signal stored in said control register.

Claim 5

A pulse generating device according to claim 1, wherein said counter is a free-run counter.

Claim 6

A pulse generating device according to claim 4, wherein said calculation unit obtains the 1A th time data by adding said first working time data to said reference time data, the 1B th time data by subtracting said 1A th time data from the period of said reset signal, the 2A th time data by subtracting said 2A th time data from said reference time data and the 2B th time data by subtracting the 2A th time data from the period of said reset signal and said transfer control unit transfers said 1A th and 2A th time data to said first and second time data registers in response to said reset signal, and transfers said 1B th and 2B th time data to said first and second time data registers in accordance with a half period of said reset signal.

Claim 7

A pulse generating device according to claim 4, wherein said calculation unit obtains the 1A th time data by adding said first working time data to said reference time data, the 1B th time data by subtracting said reference time data from the period of said reset signal and the 2B th time data by subtracting the sum of said reference time data and said second working time data from said period of said reset signal and said transfer control unit transfers said 1A th time data and said reference time data to said first and second time data registers and transfers said 1B th time data and said 2B th time data to said first and second time data registers in accordance with a half period of said reset signal.

Claim 8

A pulse generating device according to claim 4, wherein said calculation unit obtains the 1B th time data by subtracting the sum of said reference time data and said first working time data from said period of said reset signal, the 2A th time data by subtracting said second working time data from said reference time data and the 2B th time data by subtracting said reference time data from said period of said reset signal, and said transfer control unit transfers said reference time data and said 2A th time data to said first and second time data registers in response to said reset signal and transfers said 1B th and 2B time data to said first and second time data registers in accordance with a half period of said reset signal.

Claim 9

A pulse generating device according to claim 1, wherein said counter is an up/down counter and said reset signal of said counter is a countup signal and a countdown signal which are alternately supplied at a predetermined period.

Claim 10

A pulse generating device according to claim 8, wherein said calculation unit obtains first time data by adding said first working time data to said reference time data, second time data by subtracting said second working time data from said reference time data, and said transfer control unit transfers said first and second time data to said first and second time data registers.

Claim 11

A pulse generating device according to claim 8, wherein said calculation unit obtains first time data by adding said first working time data to said reference time data, second time data by subtracting said second working time data from said reference time data, and said transfer control unit transfers said first time data and said reference time data to said first and second time data registers in synchronization with said countup signal and transfers said reference time data and second time data to said first and second time data registers in synchronization with said countdown signal.

Claim 12

A pulse generating device according to claim 8, wherein said calculation unit obtains first time data by adding said first working time data to said reference time data, second time data by subtracting said second working time data from said reference time data, and said transfer control unit transfers said reference time data and said second time data to said first and second time data registers in synchronization with said countup signal and transfers said first time data and said reference time data to said first and second time data registers in synchronization with said countdown signal.

Claim 13

A pulse generating device comprising a processor and pulse generating means, said processor includes: a reference time data register for storing reference time data for defining a timing axis for a pair of pulses to be generated, first and second working time data registers for storing respectively working time data showing a time difference between both pulses of said pair of pulses to be generated and said reference time data, a calculation unit for fetching said reference time data and said working time data, and for calculating time data on a first transition for both pulses of said pair of pulses and a last transition for both pulses of said pair of pulses, and a transfer control unit for controlling transference timing of said time data for both pulses of said pair of pulses obtained in said calculation unit; said pulse generating means including: first and second pulse output registers having storage means for storing respectively status data which is a binary digit of either pulse of said pair of pulses to be generated and having output means for outputting an output pulse, a control register for storing a calculation control signal, a transfer control signal and a reset signal, a counter for counting clock pulses, first and second time data registers for storing respectively said time data for both pulses of said pair of pulses transmitted from said transfer control unit, and first and second comparators for comparing respectively said time data of both of said time data registers with the value of said counter so as to transmit a coincidence signal when said compared values coincide with each other; wherein said calculation unit performs a calculation defined in response to said calculation control signal stored in said control register, said transfer control unit controls said transference timing of each of said time data in response to said transfer control signal stored in said control register, said output means of both of said pulse output registers respectively outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when a next coincidence signal is supplied, said counter is reset in response to said reset signal periodically stored in said control register, and said reference time data, each of said working time data and said status data are supplied in synchronism with said reset signal from another processor.

Claim 14

A pulse generating device comprising a processor and pulse generating means, said processor includes: a reference time data register for storing reference time data for defining a timing axis for a pair of pulses to be generated, first and second working time data registers for storing respectively working time data showing a time difference between both pulses of said pair of pulses to be generated and said reference time data, a calculation unit for fetching said reference time data and said working time data, and for calculating time data on a first transition for both pulses of said pair of pulses and a last transition for both pulses of said pair of pulses, and a transfer control unit for controlling transference timing of said time data for both pulses of said pair of pulses obtained in said calculation unit; said pulse generating means including: first and second pulse output registers having storage means for storing respectively status data which is a binary digit of either pulse of said pair of pulses to be generated and having output means for outputting an output pulse, a control register for storing a calculation control signal, a transfer control signal and a reset signal, a counter for counting clock pulses, first and second time data registers for storing respectively said time data for both pulses of said pair of pulses transmitted from said transfer control unit, and first and second comparators for comparing respectively said time data of both of said time data registers with the value of said counter so as to transmit a coincidence signal when said compared values coincide with each other; wherein said calculation unit performs a calculation defined in response to said calculation control signal stored in said control register, said transfer control unit controls said transference timing of each of said time data in response to said transfer control signal stored in said control register, said output means of both of said pulse output registers respectively outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when a next coincidence signal is supplied, said counter is reset in response to said reset signal periodically stored in said control register, and said reference time data, each of said working time data and said status data are supplied in synchronism with said reset signal from another processor.

Claim 15

A pulse generating device according to claim 12, wherein output switches for selecting either of said output terminals of each of said pulse output registers and said inversion output terminal are provided, and each of said switches is controlled in response to an output switch control signal stored in said control register.

Claim 16

A pulse generating device according to claim 12, wherein said counter is a free-run counter.

Claim 17

A pulse generating device according to claim 14, wherein said calculation unit obtains the 1A th time data by adding said first working time data to said reference time data, the 1B th time data by subtracting said 1A th time data from the period of said reset signal, the 2A th time data by subtracting said 2A th time data from said reference time data and the 2B th time data by subtracting the 2A th time data from the period of said reset signal and said transfer control unit transfers said 1A th and 2A th time data to said first and second time data registers in response to said reset signal, and transfers said 1B th and 2B th time data to said first and second time data registers in accordance with a half period of said reset signal.

Claim 18

A pulse generating device according to claim 14, wherein said calculation unit obtains the 1A th time data by adding said first working time data to said reference time data, the 1B th time data by subtracting said reference time data from the period of said reset signal and the 2B th time data by subtracting the sum of said reference time data and said second working time data from said period of said reset signal and said transfer control unit transfers said 1A th time data and said reference time data to said first and second time data registers and transfers said 1B th time data and said 2B th time data to said first and second time data registers in accordance with a half period of said reset signal.

Claim 19

A pulse generating device according to claim 14, wherein said calculation unit obtains the 1B th time data by subtracting the sum of said reference time data and said first working time data from said period of said reset signal, the 2A th time data by subtracting said second working time data from said reference time data and the 2B th time data by subtracting said reference time data from said period of said reset signal, and said transfer control unit transfers said reference time data and said 2A th time data to said first and second time data registers in response to said reset signal and transfers said 1B th and 2B time data to said first and second time data registers in accordance with a half period of said reset signal.

Claim 20

A pulse generating device according to claim 12, wherein said counter is an up/down counter and said reset signal of said counter is a countup signal and a countdown signal which are alternately supplied at a predetermined period.

Claim 21

A pulse generating device according to claim 18, wherein said calculation unit obtains first time data by adding said first working time data to said reference time data, second time data by subtracting said second working time data from said reference time data, and said transfer control unit transfers said first and second time data to said first and second time data registers.

Claim 22

A pulse generating device according to claim 18, wherein said calculation unit obtains first time data by adding said first working time data to said reference time data, second time data by subtracting said second working time data from said reference time data, and said transfer control unit transfers said first time data and said reference time data to said first and second time data registers in synchronization with said countup signal and transfers said reference time data and second time data to said first and second time data registers in synchronization with said countdown signal.

Claim 23

A pulse generating device according to claim 18, wherein said calculation unit obtains first time data by adding said first working time data to said reference time data, second time data by subtracting said second working time data from said reference time data, and said transfer control unit transfers said reference time data and said second time data to said first and second time data registers in synchronization with said countup signal and transfers said first time data and said reference time data to said first and second time data registers in synchronization with said countdown signal.

Claim 24

A pulse generating device comprising a processor and pulse generating means, said processor includes: a reference time data register for storing reference time data for defining a timing axis of either of a pair of pulses to be generated, working time data register for storing working time data showing a time difference between either pulse of said pair of pulses to be generated and another pulse, a calculation unit for fetching said reference time data and said working time data, and for calculating time data on a first transition for both pulses of said pair of pulses and a last transition for both pulses of said pair of pulses, and a transfer control unit for controlling transference timing of said time data for both pulses of said pair of pulses obtained in said calculation unit; said pulse generating means including: first and second pulse output registers having storage means for storing respectively status data which is a binary digit to specify the binary digit status of said either pulse of said pair of pulses to be generated, and having output means for outputting an output pulse, a control register for storing a calculation control signal, a transfer control signal and a reset signal, a counter for counting clock pulses, first and second time data registers for storing respectively said time data for both pulses of said pair of pulses transmitted from said transfer control unit, and first and second comparators for comparing respectively said time data of both of said time data registers with the value of said counter so as to transmit a coincidence signal when said compared values coincide with each other; wherein said calculation unit performs a calculation defined in response to said calculation control signal stored in said control register, said transfer control unit controls said transference timing of each of said time data in response to said transfer control signal stored in said control register, said output means of said first pulse output register outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when a next coincidence signal is supplied, said output means of said second pulse output register outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when the one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when the next coincidence signal is supplied, said counter is reset in response to said reset signal periodically stored in said control register, and said reference time data, each of said working time data and said status data are supplied in synchronism with said reset signal from another processor.

Claim 25

A pulse generating device comprising a processor and pulse generating means, said processor includes: a reference time data register for storing reference time data for defining a timing axis of either of a pair of pulses to be generated, working time data register for storing working time data showing a time difference between either pulse of said pair of pulses to be generated and another pulse, a calculation unit for fetching said reference time data and said working time data, and for calculating time data on a first transition for both pulses of said pair of pulses and a last transition for both pulses of said pair of pulses, and a transfer control unit for controlling transference timing of said time data for both pulses of said pair of pulses obtained in said calculation unit; said pulse generating means including: first and second pulse output registers having storage means for storing respectively status data which is a binary digit to specify the binary digit status of said either pulse of said pair of pulses to be generated, and having output means for outputting an output pulse, a control register for storing a calculation control signal, a transfer control signal and a reset signal, a counter for counting clock pulses, first and second time data registers for storing respectively said time data for both pulses of said pair of pulses transmitted from said transfer control unit, and first and second comparators for comparing respectively said time data of both of said time data registers with the value of said counter so as to transmit a coincidence signal when said compared values coincide with each other; wherein said calculation unit performs a calculation defined in response to said calculation control signal stored in said control register, said transfer control unit controls said transference timing of each of said time data in response to said transfer control signal stored in said control register, said output means of said first pulse output register outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when a next coincidence signal is supplied, said output means of said second pulse output register outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when the one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when the next coincidence signal is supplied, said counter is reset in response to said reset signal periodically stored in said control register, and said reference time data, each of said working time data and said status data are supplied in synchronism with said reset signal from another processor.

Claim 26

A pulse generating device according to claim 22, wherein both of said pulse output registers has an inversion output terminal which is maintained at the inverted status of said output terminal.

Claim 27

A pulse generating device according to claim 22, wherein output switches for selecting either of said output terminals of each of said pulse output registers and said inversion output terminal are provided, and each of said switches is controlled in response to an output switch control signal stored in said control register.

Claim 28

A pulse generating device according to claim 22, wherein said counter is a free-run counter.

Claim 29

A pulse generating device according to claim 22, wherein said counter is an up/down counter and said reset signal of said counter is a countup signal and a countdown signal which are alternately supplied at a predetermined period.

Claim 30

A pulse generating device according to claim 26, wherein said calculation unit makes said reference time data to be first time data and obtains second time data by subtracting said working time data from said reference time data, and said transfer control unit transfers said first and second time data to said first and second time data registers.

Claim 31

A pulse generating device comprising a processor and pulse generating means, said processor includes: a reference time data register for storing reference time data for defining a timing reference of either of a pair of pulses to be generated, a working time data register for storing working time data showing a timing difference between said either pulse of said pair of pulses to be generated and another pulse, a calculation unit for fetching said reference time data and said working time data, and for calculating time data on a first transition for both pulses of said pair of pulses and a last transition for both pulses of said pair of pulses, and a transfer control unit for controlling transference timing of said time data for both pulses of said pair of pulses obtained in said calculation unit; said pulse generating means including: first and second pulse output registers having storage means for storing respectively status data which is a binary digit to specify the binary digit status of said either pulse of said pair of pulses, and having output means for outputting an output pulse, a control register for storing a calculation control signal, a transfer control signal and a reset signal, a counter for counting clock pulses, first and second time data registers for storing respectively said time data for both pulses of said pair of pulses transmitted from said transfer control unit, and first and second comparators for comparing respectively said time data for both of said time data registers with the value of said counter so as to transmit a coincidence signal when said compared values coincide with each other; wherein said calculation unit performs a calculation defined in response to said calculation control signal stored in said control register, said transfer control unit controls said transference timing of each of said time data in response to said transfer control signal stored in said control register, said output means of both of said pulse output registers respectively outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when a next coincidence signal is supplied, said counter is reset in response to said reset signal periodically stored in said control register, and said reference time data, each of said working time data and said status data are supplied in synchronism with said reset signal from another processor.

Claim 32

A pulse generating device comprising a processor and pulse generating means, said processor includes: a reference time data register for storing reference time data for defining a timing reference of either of a pair of pulses to be generated, a working time data register for storing working time data showing a timing difference between said either pulse of said pair of pulses to be generated and another pulse, a calculation unit for fetching said reference time data and said working time data, and for calculating time data on a first transition for both pulses of said pair of pulses and a last transition for both pulses of said pair of pulses, and a transfer control unit for controlling transference timing of said time data for both pulses of said pair of pulses obtained in said calculation unit; said pulse generating means including: first and second pulse output registers having storage means for storing respectively status data which is a binary digit to specify the binary digit status of said either pulse of said pair of pulses, and having output means for outputting an output pulse, a control register for storing a calculation control signal, a transfer control signal and a reset signal, a counter for counting clock pulses, first and second time data registers for storing respectively said time data for both pulses of said pair of pulses transmitted from said transfer control unit, and first and second comparators for comparing respectively said time data for both of said time data registers with the value of said counter so as to transmit a coincidence signal when said compared values coincide with each other; wherein said calculation unit performs a calculation defined in response to said calculation control signal stored in said control register, said transfer control unit controls said transference timing of each of said time data in response to said transfer control signal stored in said control register, said output means of both of said pulse output registers respectively outputs said output pulse corresponding to an inverse binary digit that is the complement of said status data when one coincidence signal is supplied from a corresponding comparator, and said output pulse corresponding to an inverse binary digit that is reset to the same state as said status data when a next coincidence signal is supplied, said counter is reset in response to said reset signal periodically stored in said control register, and said reference time data, each of said working time data and said status data are supplied in synchronism with said reset signal from another processor.

Claim 33

A pulse generating device according to claim 28, wherein each of said pulse output registers has an inversion output terminal which is maintained at the inverted status of said output terminal.

Claim 34

A pulse generating device according to claim 28, wherein output switches for selecting either of said output terminals of each of said pulse output registers and said inversion output terminal are provided, and each of said switches is controlled in response to an output switch control signal stored in said control register.

Claim 35

A pulse generating device according to claim 28, wherein said counter is a free-run counter.

Claim 36

A pulse generating device according to claim 28, wherein said counter is an up/down counter and said reset signal of said counter is a countup signal and a countdown signal which are alternately supplied at a predetermined period.

Claim 37

A pulse generating device according to claim 32, wherein said calculation unit makes said reference time data to be first time data and obtains second time data by subtracting said working time data from said reference time data and said transfer control unit transfers said first and second time data to said first and second time data registers.