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US5418752A
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Flash EEPROM system with erase sector select
Assignee: Toshiba Corp
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Filing: 1992-10-20
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Granted: 1995-05-23
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Expires: 2012-10-20
Abstract
Abstract A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
Inventors
- 👤 Eliyahou Harari
- 👤 Robert D. Norman
- 👤 Sanjay Mehrotra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:09
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0238; G06F12/0246; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0866; G06F12/0875; G06F12/12; G06F12/121; G06F12/123; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/0614; G06F3/0616; G06F3/0628; G06F3/0638; G06F3/064; G06F3/0646; G06F3/0652; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0679; G06F3/068; G06F3/0683; G06F3/0688; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C16/3459; G11C29/52; G11C29/70; G11C29/76; G11C29/765; G11C29/78; G11C29/80; G11C29/816; G11C29/82; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G11C8/00; G11C8/12; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1068; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022; G06F2212/31; G06F2212/312; G06F2212/72; G06F2212/7201; G06F2212/7203; G06F2212/7205; G06F2212/7207; G06F2212/7208; G06F3/0662; G06F3/0664; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634; G11C2211/564; G11C2211/5643; G11C2216/00; G11C2216/12; G11C2216/18; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
88 words
A Flash EEprom system comprising: one or more integrated circuit chips each having an array of Flash EEprom cells partitioned into a plurality of sectors, each sector addressable for erase such that all cells therein are erasable simultaneously; means for selecting a plurality of sectors among the one or more chips for erase operation; means for simultaneously performing the erase operation on only the plurality of selected sectors; and individual register associated with each sector for holding a status to indicate whether the sector is selected or not.
Claim 2
Dependent Claim
88 words
A Flash EEprom system comprising: one or more integrated circuit chips each having an array of Flash EEprom cells partitioned into a plurality of sectors, each sector addressable for erase such that all cells therein are erasable simultaneously; means for selecting a plurality of sectors among the one or more chips for erase operation; means for simultaneously performing the erase operation on only the plurality of selected sectors; and individual register associated with each sector for holding a status to indicate whether the sector is selected or not.
Claim 3
Dependent Claim
35 words
The Flash EEprom system according to claim 1, wherein the simultaneously erasing means is responsive to the status in each of the individual registers, such that only the selected sectors are included in the erasing.
Claim 4
Dependent Claim
28 words
The Flash EEprom system according to claim 1, wherein any one or combination of the individual registers indicating a selected status are individually resettable to an unselected status.
Claim 5
Dependent Claim
26 words
The Flash EEprom system according to claim 1, wherein all the individual registers are simultaneously resettable to a status indicating the associated sectors as not selected.
References Cited (Backward Citations)
US4752871A
Cited
US4970692A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-22 | 1998-11-21 | 1999-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-22 | 2002-11-21 | 2003-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-22 | 2006-11-21 | 2007-05-23 | $7700.00 | Window Closed / Lapsed |