Method of assembling a monolithic gallium arsenide phased array using integrated gold post interconnects

Claim 1

A method of assembling a monolithic phased array of the type having a n×m array of radiating elements and at least a first layer electrically connected to a second layer, said method comprising the steps of: a. fabricating a plurality of T/R modules from at least one wafer, each of said plurality of T/R modules having integrated thereon a plurality of gold posts for interconnecting said first layer to said second layer; b. placing a predetermined amount of solder reform on each tip of said plurality of gold posts during said fabrication of said plurality of T/R modules; c. testing said plurality of T/R module wafers according to a set of predetermined criteria and identifying each T/R module that is functional; d. selecting from said at least one wafer sub-arrays of said functional T/R modules; e. fabricating a metallic tray having a set of precision alignment marks and a plurality of slits forming a n×m array corresponding to said n×m array of radiating elements; f. populating said metallic tray with said sub-arrays of said functional T/R modules such that said sub-arrays of T/R modules are mounted on said metallic tray in alignment with said precision alignment marks on said metallic tray, said populated metallic tray constituting said first layer; g. placing a distribution network substrate which constitutes said second layer on said first layer; h. heating the thus assembled phased array to the melting point of said solder reform disposed on said gold posts; and i. cooling the thus heated assembled phased array causing said second layer to be electrically connected to said first layer thereby forming said monolithic phased array.

Claim 2

A method of assembling a monolithic phased array of the type having a n×m array of radiating elements and at least a first layer electrically connected to a second layer, said method comprising the steps of: a. fabricating a plurality of T/R modules from at least one wafer, each of said plurality of T/R modules having integrated thereon a plurality of gold posts for interconnecting said first layer to said second layer; b. placing a predetermined amount of solder reform on each tip of said plurality of gold posts during said fabrication of said plurality of T/R modules; c. testing said plurality of T/R module wafers according to a set of predetermined criteria and identifying each T/R module that is functional; d. selecting from said at least one wafer sub-arrays of said functional T/R modules; e. fabricating a metallic tray having a set of precision alignment marks and a plurality of slits forming a n×m array corresponding to said n×m array of radiating elements; f. populating said metallic tray with said sub-arrays of said functional T/R modules such that said sub-arrays of T/R modules are mounted on said metallic tray in alignment with said precision alignment marks on said metallic tray, said populated metallic tray constituting said first layer; g. placing a distribution network substrate which constitutes said second layer on said first layer; h. heating the thus assembled phased array to the melting point of said solder reform disposed on said gold posts; and i. cooling the thus heated assembled phased array causing said second layer to be electrically connected to said first layer thereby forming said monolithic phased array.