Low skew system for interfacing asics by routing internal clock off-chip to external delay element then feeding back to on-chip drivers

Claim 2

An interface system for enabling an ASIC chip's drivers and receivers to qualify information communicated on one or more buses such that skew is minimized, the ASIC chip having an internal clock, the interface comprising: driver means located on the ASIC chip for generating a clock signal with a phase different from the phase of the internal clock and routing said clock signal off-chip into a delay element; and delay means located off the chip for delaying said clock signal using said delay element to thereby generate a qualifying clock signal and routing said qualifying clock signal back on-chip to qualify information being driven to or information being latched from the one or more buses.

Claim 3

A system according to claim 1, wherein said qualifying clock signal is used to enable at least one on-chip receiver to latch information from the one or more buses into the chip.

Claim 4

A system according to claim 1, wherein said qualifying clock signal is used to enable at least one on-chip driver to transfer information from the ASIC chip to the one or more buses.

Claim 5

A system according to claim 2, further comprising: further driver means for generating a plurality of clock signals each with a phase different from the phase of the internal clock and routing said plurality of clock signals off-chip into a plurality of delay elements; and further delay means for delaying said plurality of clock signals using said delay elements to thereby generate a plurality of latch clock signals and routing said plurality of latch clock signals back on-chip to a plurality of on-chip receivers to transfer information from the one or more buses to the ASIC chip.

Claim 6

A system according to claim 3, further comprising; further driver means for generating a plurality of clock signals each with a phase different from the phase of the internal clock and routing said plurality of clock signals off-chip into a plurality of delay elements; and further delay means for delaying said plurality of clock signals using said delay elements to thereby generate a plurality of drive clock signals and routing said plurality of drive clock signals back on-chip to a plurality of on-chip drivers to transfer information from the ASIC chip to the one or more buses.

Claim 7

A system according to claim 2, further comprising: a further driver means for generating a further of clock signal with a phase different from the phase of the internal clock and routing said further clock signal off-chip into a further delay element; and a further delay means for delaying said further clock signal using said further delay element to thereby generate a further qualifying clock signal and routing said further qualifying clock signal to one of a further receiver on another chip to transfer information from the one or more buses to said another chip, or a further driver on said another chip to transfer information from said another chip to the one or more buses.

Claim 10

A method according to claim 7, wherein said qualifying clock signal is used to enable at least one on-chip receiver to latch information from the one or more buses into the ASIC chip.

Claim 11

A method according to claim 7, wherein said qualifying clock signal is used to enable at least one on-chip driver to transfer information from the ASIC chip to the one or more buses.

Claim 12

A method according to claim 8, further comprising the steps of: generating a plurality of clock signals each with a phase different from the phase of the internal clock; routing said plurality of clock signals off-chip into a plurality of delay elements, respectively; delaying said plurality of clock signals using said delay elements to thereby generate a plurality of latch clock signals; and routing said plurality of latch clock signals back on-chip to a plurality of on-chip receivers to transfer information from the one or more buses to the ASIC chip.

Claim 13

A method according to claim 9, further comprising the steps of: generating a plurality of clock signals each with a phase different from the phase of the internal clock; routing said plurality of clock signals off-chip into a plurality of delay elements, respectively; delaying said plurality of clock signals using said delay elements to thereby generate a plurality of drive clock signals; and routing said plurality of drive clock signals back on-chip to a plurality of on-chip drivers to transfer information from the ASIC chip to the one or more buses.

Claim 14

A method according to claim 8, further comprising the steps of: generating a plurality of clock signals each with a phase different from the phase of the internal clock; routing said plurality of clock signals off-chip into a plurality of delay elements, respectively; delaying said plurality of clock signals using said delay elements to thereby generate a plurality of latch clock signals; and routing said plurality of latch clock signals to a plurality of receivers on a further chip to transfer information from the one or more buses to the further chip.

Claim 15

A method according to claim 9, further comprising the steps of: generating a plurality of clock signals each with a phase different from the phase of the internal clock; routing said plurality of clock signals off-chip into a plurality of delay elements, respectively; delaying said plurality of clock signals using said delay elements to thereby generate a plurality of drive clock signals; and routing said plurality of drive clock signals to a plurality of further drivers on a further chip to transfer information from the further chip to the one or more buses.

Claim 16

An interface system for enabling an ASIC chip's drivers and receivers located on the ASIC chip to qualify information communicated on one or more buses such that skew is minimized, the ASIC chip having an internal clock, the system comprising: a driver circuit connected to the internal clock and located on the ASIC chip for generating a clock signal with a phase different from the phase of the internal clock; a delay element located off the ASIC chip and connected to said driver circuit for delaying said clock signal thereby generating at least one of a drive clock signal and a latch clock signal; and means for conducting said drive clock signal to the drivers located on the ASIC chip to transfer information from the ASIC chip to the one or more buses, or for conducting said latch clock signal to the receivers located on the ASIC chip to transfer information from the one ore more buses to the chip.

Claim 17

An interface system for enabling an ASIC chip's drivers and receivers located on the ASIC chip to qualify information communicated on one or more buses such that skew is minimized, the ASIC chip having an internal clock, the system comprising: a driver circuit connected to the internal clock and located on the ASIC chip for generating a clock signal with a phase different from the phase of the internal clock; a delay element located off the ASIC chip and connected to said driver circuit for delaying said clock signal thereby generating at least one of a drive clock signal and a latch clock signal; and means for conducting said drive clock signal to the drivers located on the ASIC chip to transfer information from the ASIC chip to the one or more buses, or for conducting said latch clock signal to the receivers located on the ASIC chip to transfer information from the one ore more buses to the chip.

Claim 18

A system according to claim 14, wherein said driver circuit comprises: an output pad for transferring said clock signal to said delay element; an invertor for inverting the internal clock; a first transistor, controlled by the output of said invertor, for connecting said pad to a first voltage level when the internal clock in a first logic state; and a second transistor, controlled by the internal clock, for connecting said pad to a second voltage level when the internal clock in a second logic state.

Claim 19

A system according to claim 14, wherein said system further includes: a plurality of driver circuits connected to the internal clock for generating a plurality of clock signals each with a phase different from the phase of the internal clock; a plurality of delay elements located off the chip, each connected to one of said plurality of driver circuits for delaying said respective clock signal thereby generating a plurality of drive or latch clock signals; and further means for conducting said drive clock signals to the drivers located on the ASIC chip to transfer information from the chip to the one or more buses, or for conducting said latch clock signals to the receivers located on the ASIC chip to transfer information from the one or more buses to the chip.

Claim 20

A system according to claim 14, wherein said system further includes: a further driver circuit connected to the internal clock for generating a further clock signal with a phase different from the phase of the internal clock; a further delay element located off the chip and connected to said further driver circuit for delaying said further clock signal thereby generating a further drive or a further latch clock signal; and further means for conducting said drive clock signal to further drivers located on another chip to transfer information from said another chip to the one or more buses, or for conducting said further latch clock signal to further receivers on said another chip to transfer information from the one or more buses to said another chip.

Claim 21

A system according to claim 15, wherein said delay element comprises a metal trace which forms a wire on a printed circuit board.

Claim 22

A system according to claim 15, wherein said delay element comprises an electrical component having a first terminal, a second terminal, and means for connecting said first terminal to said second terminal such that a signal input to said first terminal is delayed by a predetermined amount of time before appearing at said second terminal.