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US5414831A
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US
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Apparatus and method for accessing a plurality of computer devices having a common address
Assignee: LSI Corp
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Filing: 1993-12-30
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Granted: 1995-05-09
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Expires: 2013-12-30
Abstract
Abstract An apparatus and method for accessing a plurality of computer devices having common memory or input-output addresses on buses operating at different speeds. The present invention detects a CPU address request and issues a local bus acknowledge thereto which prevents the CPU core logic from processing the instruction on the other buses. The present invention processes the instruction and upon completion thereof, asserts both CPU BOFF and READY signals on the computer system local bus. The CPU receives the BOFF signal, releases control of the local bus and ignores the READY signal. When the present invention releases the asserted BOFF signal, it then ignores the next local bus cycle because this next local bus signal will be the same as the previous bus cycle. The next CPU bus cycle contains the same information as the previous cycle, and the computer system core logic issues appropriate commands to the other bus interface such as an ISA bus. The present invention monitors the CPU READY signal and, once detected, the present invention re-enables its local bus decode logic in anticipation of the next CPU bus cycle.
Inventors
- 👤 Thomas J. Wilson
- 👤 J. Peter Van Baarsen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:54
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/404
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
272 words
A method for writing data to two or more computer devices having common addresses but on different computer system buses, comprising the steps of: (a) asserting computer device addresses and data on the computer system buses by the computer system central processing unit (CPU); (b) asserting a first acknowledge signal on a first bus of the computer system buses by a first bus computer device when predefined addresses match the asserted computer device addresses, wherein the asserted first acknowledge signal prevents the computer system core logic from processing the computer device addresses and data on a second bus; (c) processing the asserted addresses and data by the first bus computer device; (d) asserting a backoff signal on the first bus by the first bus computer device which causes the CPU to repeat the same computer device addresses and data on the computer system buses as was asserted in step (a); (e) reasserting the same computer device addresses and data as was asserted in step (a) on the computer system buses by the CPU, wherein the first bus computer device now ignores the addresses and data on the first bus and the second bus computer device processes the reasserted addresses and data on a second bus of the computer system buses when predefined addresses match the reasserted computer device addresses; and (f) resetting the first bus computer device after the second bus computer device asserts an acknowledge signal to the CPU that it has processed the reasserted addresses and data of step (e), wherein the first bus computer device is ready to process next computer device addresses and data asserted by the CPU.
Claim 2
Independent Claim
272 words
A method for writing data to two or more computer devices having common addresses but on different computer system buses, comprising the steps of: (a) asserting computer device addresses and data on the computer system buses by the computer system central processing unit (CPU); (b) asserting a first acknowledge signal on a first bus of the computer system buses by a first bus computer device when predefined addresses match the asserted computer device addresses, wherein the asserted first acknowledge signal prevents the computer system core logic from processing the computer device addresses and data on a second bus; (c) processing the asserted addresses and data by the first bus computer device; (d) asserting a backoff signal on the first bus by the first bus computer device which causes the CPU to repeat the same computer device addresses and data on the computer system buses as was asserted in step (a); (e) reasserting the same computer device addresses and data as was asserted in step (a) on the computer system buses by the CPU, wherein the first bus computer device now ignores the addresses and data on the first bus and the second bus computer device processes the reasserted addresses and data on a second bus of the computer system buses when predefined addresses match the reasserted computer device addresses; and (f) resetting the first bus computer device after the second bus computer device asserts an acknowledge signal to the CPU that it has processed the reasserted addresses and data of step (e), wherein the first bus computer device is ready to process next computer device addresses and data asserted by the CPU.
Claim 3
Dependent Claim
279 words
A computer interface first device adapted for connection to a first bus of a computer system central processing unit (CPU) that functions with a second device connected to a second bus of the computer system and both configured to respond to the same addresses and receive the same data, said first device comprising: first logic circuits for detecting addresses and data asserted by the CPU on the first and second buses, said first logic asserting an acknowledge signal on the first bus when predefined addresses are detected, wherein the acknowledge signal prevents the second device from processing the addresses and data asserted by the CPU on the second bus; second logic circuits for asserting a back off signal on the first bus after the first device has finished processing the addresses and data asserted by the CPU, wherein the back off signal causes the CPU to repeat the same addresses and data on the first and second buses so that the second device can now process the same addresses and data asserted by the CPU; said second logic circuits also disables the first logic so that the first device ignores the same addresses and data assert by the CPU during the repeat of the same addresses and data by the CPU on the first and second buses; and third logic circuits for detecting the completion of processing of the same addresses and data by the second device, wherein after said third logic circuit detects the completion of the processing of the same addresses and data by the second device, said first device is re-enabled so that the first device can process next addresses and data asserted by the CPU.
Claim 4
Dependent Claim
279 words
A computer interface first device adapted for connection to a first bus of a computer system central processing unit (CPU) that functions with a second device connected to a second bus of the computer system and both configured to respond to the same addresses and receive the same data, said first device comprising: first logic circuits for detecting addresses and data asserted by the CPU on the first and second buses, said first logic asserting an acknowledge signal on the first bus when predefined addresses are detected, wherein the acknowledge signal prevents the second device from processing the addresses and data asserted by the CPU on the second bus; second logic circuits for asserting a back off signal on the first bus after the first device has finished processing the addresses and data asserted by the CPU, wherein the back off signal causes the CPU to repeat the same addresses and data on the first and second buses so that the second device can now process the same addresses and data asserted by the CPU; said second logic circuits also disables the first logic so that the first device ignores the same addresses and data assert by the CPU during the repeat of the same addresses and data by the CPU on the first and second buses; and third logic circuits for detecting the completion of processing of the same addresses and data by the second device, wherein after said third logic circuit detects the completion of the processing of the same addresses and data by the second device, said first device is re-enabled so that the first device can process next addresses and data asserted by the CPU.
Claim 5
Dependent Claim
26 words
The apparatus of claim 2, wherein the first device is a local bus video graphics adapter and the first bus is a computer system local bus.
Claim 6
Dependent Claim
30 words
The apparatus of claim 2, wherein the second device is an industry standard architecture bus video graphics adapter and the second bus is a computer system industry standard architecture bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-08 | 1998-11-07 | 1999-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-08 | 2002-11-07 | 2003-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-08 | 2006-11-07 | 2007-05-09 | $7700.00 | Window Closed / Lapsed |