US5414383A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four quadrant multiplier circuit and a receiver including such a circuit
Assignee: US Philips Corp
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Filing: 1994-02-24
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Granted: 1995-05-09
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Expires: 2014-02-24
Abstract
Abstract A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages includes a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each Darlington circuit includes first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69). The emitter currents of the dual transconductance amplifier are supplied by way of current mirror circuits (80,81) from the emitter currents of the second transistors (70,71). The transconductance amplifier circuit (TAC) may be of any suitable type which has its transconductance linearly proportional to its emitter currents. In a refinement of the circuit, the current-to-voltage converter function of the current mirrors is carried out by the second transistors (70,71) and the transistors (82,83) of the current mirror circuits (80,81) are omitted.
Inventors
- 👤 Anthony R. Cusdin
- 👤 Paul A. Moore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:22
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/007; H03D7/00; H03D7/14; H03D7/1408; H03D7/1425; H03D7/1433; H03D7/1458; H03D7/1491; H03D7/16; H03D7/165; H03D2200/00; H03D2200/0001; H03D2200/0019; H03D2200/0033
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
222 words
A four quadrant multiplier circuit comprising first and second input ports and first and second circuits coupled respectively to the first and second input ports, said second circuit converting voltages applied at the second input port to currents which are supplied to the first circuit, characterized in that the first circuit comprises a dual transconductance amplifier whose transconductance is linearly proportional to currents supplied by the second circuit, the dual transconductance amplifier comprising transistors of a first conductivity type, and in that the second circuit comprises first and second folded Darlington circuits, each folded Darlington circuit comprising first and second transistors of a first conductivity type whose emitter-collector paths are connected in series, and a third transistor of a second conductivity type having its emitter collector path connected between the collector of the first transistor and the base of the second transistor, the junction of the emitter of the first transistor and the collector of the second transistor being connected to the base electrode of the third transistor, the second input port being connected to the base electrodes of the first transistors, and a resistive element connected between the base electrodes of the third transistors, wherein the currents supplied to the dual transconductance amplifier are derived by way of respective current mirror circuits from the emitter currents of the respective second transistors.
Claim 2
Dependent Claim
222 words
A four quadrant multiplier circuit comprising first and second input ports and first and second circuits coupled respectively to the first and second input ports, said second circuit converting voltages applied at the second input port to currents which are supplied to the first circuit, characterized in that the first circuit comprises a dual transconductance amplifier whose transconductance is linearly proportional to currents supplied by the second circuit, the dual transconductance amplifier comprising transistors of a first conductivity type, and in that the second circuit comprises first and second folded Darlington circuits, each folded Darlington circuit comprising first and second transistors of a first conductivity type whose emitter-collector paths are connected in series, and a third transistor of a second conductivity type having its emitter collector path connected between the collector of the first transistor and the base of the second transistor, the junction of the emitter of the first transistor and the collector of the second transistor being connected to the base electrode of the third transistor, the second input port being connected to the base electrodes of the first transistors, and a resistive element connected between the base electrodes of the third transistors, wherein the currents supplied to the dual transconductance amplifier are derived by way of respective current mirror circuits from the emitter currents of the respective second transistors.
Claim 3
Dependent Claim
23 words
A multiplier circuit as claimed in claim 1, characterized in that the current-to-voltage converters of the current mirror circuits comprise the second transistors.
Claim 4
Dependent Claim
26 words
A multiplier circuit as claimed in claim 1, characterized in that a capacitive element is connected between the emitter and collector electrodes of each third transistor.
Claim 5
Dependent Claim
67 words
A multiplier circuit as claimed in claim 1, characterized by each of the first and second Darlington circuits having a fourth transistor of the second conductivity type, the emitter and base electrodes of the fourth transistors being connected, respectively, to the collector and base electrodes of the first transistor and the collector electrode of the fourth transistor being connected to the base electrode of the second transistor.
Claim 6
Dependent Claim
21 words
A multiplier circuit as claimed in claim 1, characterized in that the dual transconductance amplifier comprises a dual class-AB transconductance amplifier.
Claim 7
Dependent Claim
200 words
A multiplier circuit as claimed in claim 1, characterized in that the dual transconductance amplifier comprises fifth and sixth transistors having collector electrodes connected to respective resistive elements, base electrodes connected to the first input port and emitter electrodes connected to a first junction which is connected to one of the current mirror circuits, seventh and eighth transistors having base electrodes respectively connected to the base electrodes of the fifth and sixth transistors, emitter electrodes connected to a second junction which is connected to the other of the current mirror circuits, collector electrodes of the seventh and eighth transistors being connected to the collector electrode of the sixth and fifth transistors, respectively, a tapped resistive element having first and second ends connected respectively to the base electrodes of the fifth and seventh transistors and of the sixth and eighth transistors, each tap of the resistive element comprising base electrodes of pairs of transistors, collector electrodes of the transistors of each pair being coupled to a supply voltage line, an emitter electrode of one transistor of each pair being connected to the first junction and an emitter electrode of the other transistor of each pair being connected to the second junction.
Claim 8
Dependent Claim
246 words
A FM receiver having a signal input, means for producing quadrature related zero IF signals and demodulating means for producing an output signal, the demodulating means comprising at least one four quadrant multiplier circuit comprising first and second input ports and first and second circuits coupled, respectively, to the first and second input ports, said second circuit converting voltages applied to the second input port to currents which are supplied to the first circuit, characterized in that the first circuit comprises a dual transconductance amplifier whose transconductance is linearly proportional to currents supplied by the second circuit, the dual transconductance amplifier comprising transistors of a first conductivity type, and in that the second circuit comprises first and second folded Darlington circuits, each folded Darlington circuit comprising first and second transistors of a first conductivity type whose emitter-collector paths are connected in series, and a third transistor of a second conductivity type having its emitter-collector path connected between the collector of the first transistor and the base of the second transistor, the junction of the emitter of the first transistor and the collector of the second transistor being connected to the base electrode of the third transistor, the second input port being connected to the base electrodes of the first transistors, and a resistive element connected between the base electrodes of the third transistors, wherein the currents supplied to the dual transconductance amplifier are derived by way of respective current mirror circuits from the respective second transistors.
Claim 9
Dependent Claim
246 words
A FM receiver having a signal input, means for producing quadrature related zero IF signals and demodulating means for producing an output signal, the demodulating means comprising at least one four quadrant multiplier circuit comprising first and second input ports and first and second circuits coupled, respectively, to the first and second input ports, said second circuit converting voltages applied to the second input port to currents which are supplied to the first circuit, characterized in that the first circuit comprises a dual transconductance amplifier whose transconductance is linearly proportional to currents supplied by the second circuit, the dual transconductance amplifier comprising transistors of a first conductivity type, and in that the second circuit comprises first and second folded Darlington circuits, each folded Darlington circuit comprising first and second transistors of a first conductivity type whose emitter-collector paths are connected in series, and a third transistor of a second conductivity type having its emitter-collector path connected between the collector of the first transistor and the base of the second transistor, the junction of the emitter of the first transistor and the collector of the second transistor being connected to the base electrode of the third transistor, the second input port being connected to the base electrodes of the first transistors, and a resistive element connected between the base electrodes of the third transistors, wherein the currents supplied to the dual transconductance amplifier are derived by way of respective current mirror circuits from the respective second transistors.
Claim 10
Dependent Claim
22 words
A receiver as claimed in claim 7, characterized in that the current-to-voltage converters of the current mirror circuits comprise the second transistors.
Claim 11
Dependent Claim
25 words
A receiver as claimed in claim 7, characterized in that a capacitive element is connected between the emitter and collector electrodes of each third transistor.
Claim 12
Dependent Claim
66 words
A receiver as claimed in claim 7, characterized by each of the first and second Darlington circuits comprising a fourth transistor of the second conductivity type, the emitter and base electrodes of the fourth transistors being connected, respectively, to the collector and base electrodes of the first transistor and the collector electrode of the fourth transistor being connected to the base electrode of the second transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-08 | 1998-11-07 | 1999-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-08 | 2002-11-07 | 2003-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-08 | 2006-11-07 | 2007-05-09 | $7700.00 | Window Closed / Lapsed |