Patent US5412596A successfully refreshed from Google Patents.
US5412596A
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US
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Semiconductor storage device with a ferroelectric transistor storage cell
Assignee: Rohm Co Ltd
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Filing: 1994-04-28
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Granted: 1995-05-02
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Expires: 2014-04-28
Abstract
Abstract A semiconductor storage device having a memory array composed of storage ceils arranged in a matrix. The storage cells include a ferroelectric transistor having a metal-ferroelectrics-semiconductor structure and a switching transistor. A source electrode of one of the transistors and a drain electrode of the other transistors are connected to each other. According to the present invention, the necessary time for writing becomes short, realizing a rapid operation of nano second order. Further, many times (1010 order) of rewriting is possible. This brings a longer life thereof compared with a EEPROM which is rewritable about 104 times. Since the reading out is non-destructive, the rewriting is not required so that the life of the device is further lengthened.
Inventors
- 👤 Kazuhiro Hoshiba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/223; H; H10; H10B; H10B53/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
135 words
A semiconductor storage device having a memory array composed of storage cells arranged in a matrix on a semiconductor substrate, said storage cells each comprising: a ferroelectric transistor having source and drain regions provided in said semiconductor substrate, a ferroelectric film provided directly on a surface of said semiconductor substrate between said source and drain regions, and a first gate electrode provided on said ferroelectric film, said ferroelectric transistor to store information by utilizing residual polarization of said ferroelectric film; and a switching transistor having a channel region provided in said semiconductor substrate and adjacent to said ferroelectric transistor, and a second gate electrode provided over both the channel region and said first gate electrode; wherein a source electrode of one of the two transistors is connected to a drain electrode of the other transistor.
Claim 2
Dependent Claim
135 words
A semiconductor storage device having a memory array composed of storage cells arranged in a matrix on a semiconductor substrate, said storage cells each comprising: a ferroelectric transistor having source and drain regions provided in said semiconductor substrate, a ferroelectric film provided directly on a surface of said semiconductor substrate between said source and drain regions, and a first gate electrode provided on said ferroelectric film, said ferroelectric transistor to store information by utilizing residual polarization of said ferroelectric film; and a switching transistor having a channel region provided in said semiconductor substrate and adjacent to said ferroelectric transistor, and a second gate electrode provided over both the channel region and said first gate electrode; wherein a source electrode of one of the two transistors is connected to a drain electrode of the other transistor.
Claim 3
Dependent Claim
134 words
The semiconductor device of claim 1, wherein the memory array comprises a first word line, a second word line, a bit line and a source line, the first word line connecting gate electrodes of switching transistors in one lateral or longitudinal line of the array; the second word line connecting gate electrodes of ferroelectric transistors in one lateral or longitudinal line of the array; the bit line connecting drain electrodes of one of said switching or ferroelectric transistors of which source electrodes are connected to drain electrodes of the other one of said switching or ferroelectric transistors in one longitudinal or lateral line which is perpendicular to the second word line; and the source line connecting source electrodes of said other one of said switching or ferroelectric transistors and said semiconductor substrate to ground.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-01 | 1998-10-31 | 1999-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-01 | 2002-10-31 | 2003-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-01 | 2006-10-31 | 2007-05-02 | $7700.00 | Window Closed / Lapsed |