PLL clock generator integrated with microprocessor

Claim 1

A phase locked loop deskewed clock generator for generating a clock signal for internal use by a microprocessor from an external clock source which generates an external clock signal wherein said clock generator forms an integrated circuit with said microprocessor, said clock generator comprising: a) clock driver means for generating an internal clock signal for internal use by said microprocessor; b) phase frequency detector means for detecting a phase difference between said external clock signal and said internal clock signal and generating a phase error signal with a pulse width having a duration equal to an amount of time the internal clock signal leads or lags the external clock signal; c) charge pump means for receiving said phase error signal and creating a control voltage change caused by a packet of charge equal to the amount of time the internal clock signal leads or lags the external clock signal; d) loop filter means for receiving and stabilizing the control voltage generated by the charge pump; e) voltage controlled oscillator means for receiving the stabilized control voltage and generating an intermediate clock signal having a predetermined frequency, said voltage controlled oscillator including: i) a voltage to current converter means coupled to said loop filter means for converting said stabilized control voltage to a first current bias signal; ii) replica biasing means coupled to said voltage to current converter means for generating a second current bias signal; iii) delay stage means coupled to said voltage to current converter means and said replica biasing means for generating a differential signal representing differences between said first current bias signal and said second current bias signal; iv) voltage swing reference generator means coupled to said replica biasing means for generating a voltage bias signal which tracks with process variations in said replica biasing means and said delay stage means; v) amplifier means coupled to said delay stage means for converting the differential signal generated by said delay stage means to a large swing, high frequency clock signal; f) means for generating a clock driver control signal as a function of said intermediate clock signal for controlling said clock driver.