Patent US5411908A successfully refreshed from Google Patents.
US5411908A
Expired / Lapsed
US
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Flash EEPROM array with P-tank insulated from substrate by deep N-tank
Assignee: Texas Instruments Inc
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Filing: 1992-05-28
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Granted: 1995-05-02
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Expires: 2012-05-28
Abstract
Abstract In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.
Inventors
- 👤 Giovanni Santin
- 👤 Giovanni Naso
- 👤 Sebastiano D'Arrigo
- 👤 Michael C. Smayling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:57
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
102 words
A method for making a nonvolatile, floating-gate memory in a face of a semiconductor body of a first conductivity-type, comprising the steps of: forming a first diffusion region in said semiconductor body, said first diffusion region doped to have a second conductivity-type opposite said first conductivity-type; forming a second diffusion region in said first diffusion region and in said semiconductor body, said second diffusion region doped to have said first conductivity-type; forming an array of floating-gate memory cells in and on said second diffusion region; and forming wordline driver circuitry in and on said semiconductor body outside of said first diffusion region.
Claim 2
Independent Claim
102 words
A method for making a nonvolatile, floating-gate memory in a face of a semiconductor body of a first conductivity-type, comprising the steps of: forming a first diffusion region in said semiconductor body, said first diffusion region doped to have a second conductivity-type opposite said first conductivity-type; forming a second diffusion region in said first diffusion region and in said semiconductor body, said second diffusion region doped to have said first conductivity-type; forming an array of floating-gate memory cells in and on said second diffusion region; and forming wordline driver circuitry in and on said semiconductor body outside of said first diffusion region.
Claim 3
Dependent Claim
33 words
The method according to claim 1, wherein said semiconductor body is silicon of P conductivity-type, said first diffusion region is of N conductivity-type and said second diffusion region is of P conductivity type.
Claim 4
Dependent Claim
32 words
The method according to claim 1 further including said semiconductor body having a first potential, wherein said first diffusion region is connected to a non-negative potential with respect to said first potential.
Claim 5
Dependent Claim
28 words
The method according to claim 1, wherein said floating-gate memory has a primary power supply and wherein said first diffusion region is connected to said primary power supply.
Claim 6
Dependent Claim
40 words
The method according to claim 1 further including said semiconductor body having a first potential, wherein during programming operation, said second diffusion region is connected to a source of second potential that is negative with respect to said first potential.
Claim 7
Dependent Claim
38 words
The method according to claim 1, wherein during programming operation, said second diffusion region is connected to a charge pump voltage supply having an output voltage that is negative with respect to the voltage of said semiconductor body.
Claim 8
Dependent Claim
19 words
The method according to claim 1, wherein Fowler-Nordheim tunnelling is used to program said floating gates of memory cells.
Claim 9
Dependent Claim
26 words
The method according to claim 1, wherein said wordline driver circuitry operates at a maximum voltage less than the voltage required to program said floating-gate memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-01 | 1998-10-31 | 1999-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-01 | 2002-10-31 | 2003-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-01 | 2006-10-31 | 2007-05-02 | $7700.00 | Window Closed / Lapsed |