Patent US5410718A successfully refreshed from Google Patents.
US5410718A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single-chip microcomputer having a memory including a one-bit memory element which has 3 inputs and a selector for selecting one of the inputs
Assignee: Renesas Electronics Corp
•
Filing: 1991-11-22
•
Granted: 1995-04-25
•
Expires: 2011-11-22
Abstract
Abstract A single-chip microcomputer includes a microprocessor, a subprocessor for performing peripheral functions, an external port for controlling an input/output operation from/to an external device and a multi-functional logic-in-memory for inputting a plurality of data from at least one of the microprocessor, the subprocessor and the external port and selecting write data from among the plurality of data in accordance with predetermined priorities.
Inventors
- 👤 Shigeki Masumura
- 👤 Tatsuya Aizawa
- 👤 Kazuo Naito
- 👤 Yoshiyuki Miwa
- 👤 Hideo Nakamura
- 👤 Terumi Sawase
- 👤 Yasushi Akao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:41
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F15/7807; G06F15/7814
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
94 words
A single-chip microcomputer comprising: a microprocessor; a subprocessor for peripheral functions; a first port for controlling an input/output operation; a memory including a plurality of 1-bit memory elements; each of said plurality of 1-bit memory elements has three separate inputs including a first input for receiving data from said microprocessor, a second input for receiving data from said subprocessor, a third input for receiving data from said first port and each of the 1-bit memory elements has a selector which selects data from either one of said microprocessor, said subprocessor and said first port.
Claim 2
Dependent Claim
94 words
A single-chip microcomputer comprising: a microprocessor; a subprocessor for peripheral functions; a first port for controlling an input/output operation; a memory including a plurality of 1-bit memory elements; each of said plurality of 1-bit memory elements has three separate inputs including a first input for receiving data from said microprocessor, a second input for receiving data from said subprocessor, a third input for receiving data from said first port and each of the 1-bit memory elements has a selector which selects data from either one of said microprocessor, said subprocessor and said first port.
Claim 3
Dependent Claim
67 words
The single-chip microprocessor according to claim 1 further comprising: a column selecting circuit and a row selecting circuit, wherein said plurality of 1-bit memory elements are arranged in a matrix manner and each of said plurality of 1-bit memory elements is selected in accordance with a combination of a column selecting signal from said column selecting circuit and a row selecting signal from said row selecting circuit.
Claim 4
Dependent Claim
24 words
The single-chip microcomputer according to claim 1, wherein said subprocessor can perform multiple accesses to different addresses of said memory at a same time.
Claim 5
Dependent Claim
20 words
The single-chip microcomputer according to claim 1, wherein said subprocessor can execute a plurality of tasks in a time-divisional manner.
Claim 6
Dependent Claim
40 words
The single-chip microcomputer according to claim 1, wherein at least one of said 1-bit memory elements is written at a digital value "0" after said microprocessor reads out a digital value "1" from said at least one 1-bit memory element.
Claim 7
Dependent Claim
38 words
The single-chip microcomputer according to claim 1, wherein said microprocessor reads out data from a register provided in said subprocessor and the data held in the register is not changed even by the reading operation by said microcomputer.
Claim 8
Dependent Claim
54 words
The single-chip microcomputer according to claim 1, wherein said selector selects data from either one of said microprocessor, said subprocessor and said first port in accordance with predetermined priorities therein when write accesses to the 1-bit memory element from at least two of said microprocessor, said subprocessor and said first port conflict each other.
Claim 9
Dependent Claim
22 words
The single-chip microcomputer according to claim 1 wherein a control circuit for performing desired functions is provided for each 1-bit memory element.
References Cited (Backward Citations)
US5206945A
Cited
US5179694A
Cited
US5175840A
Cited
US5179689A
Cited
US5321845A
Cited
US5101498A
Cited
US5093909A
Cited
US5097445A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-24 | 1998-10-24 | 1999-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-24 | 2002-10-24 | 2003-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-24 | 2006-10-24 | 2007-04-25 | $7700.00 | Window Closed / Lapsed |