Patent US5409846A successfully refreshed from Google Patents.
US5409846A
Expired / Lapsed
US
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Method of fabricating a semiconductor device including heterojunction bipolar transistor
Assignee: Panasonic Holdings Corp
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Filing: 1993-12-30
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Granted: 1995-04-25
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Expires: 2013-12-30
Abstract
Abstract A semiconductor device or an integrated circuit includes a heterojunction bipolar transistor. The transistor includes an emitter region, a base region, and a transistor electrode. The emitter region is made of first material having a first forbidden band gap. The base region is made of second material having a second forbidden band gap. The first forbidden band gap is wider than the second forbidden band gap. The transistor electrode is made of third material. A capacitor includes a plurality of capacitor electrodes which contain a capacitor electrode made of the third material. The transistor and the capacitor are electrically connected.
Inventors
- 👤 Takashi Hirose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:29
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/05
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
125 words
A method of fabricating a semiconductor device, comprising the steps of: forming a multi-layer structure on a substrate, the multi-layer structure including a collector layer, a base layer, and an emitter layer, the emitter layer being made of material having a forbidden band gap wider than a forbidden band gap of material for the base layer; exposing a portion of the base layer; simultaneously forming a collector electrode and a first capacitor electrode, the collector electrode being electrically connected to the collector layer and having an upper surface in a height position approximately equal to a height position of a surface of the exposed portion of the base layer; and forming wiring lines which include a second capacitor electrode opposed to the first capacitor electrode.
Claim 2
Independent Claim
125 words
A method of fabricating a semiconductor device, comprising the steps of: forming a multi-layer structure on a substrate, the multi-layer structure including a collector layer, a base layer, and an emitter layer, the emitter layer being made of material having a forbidden band gap wider than a forbidden band gap of material for the base layer; exposing a portion of the base layer; simultaneously forming a collector electrode and a first capacitor electrode, the collector electrode being electrically connected to the collector layer and having an upper surface in a height position approximately equal to a height position of a surface of the exposed portion of the base layer; and forming wiring lines which include a second capacitor electrode opposed to the first capacitor electrode.
Claim 3
Dependent Claim
88 words
The method of claim 1, wherein said step of forming wiring-lines comprises simultaneously forming a first wiring line, electrically connected to the emitter layer and including the second capacitor electrode, and a second wiring line, including a capacitor-electrode connecting line, and further comprising the step of simultaneously forming a third wiring line, including a third capacitor electrode opposed to the second capacitor electrode and electrically connected to the first capacitor electrode via the capacitor-electrode connecting line, and a fourth wiring line, electrically connected to the first wiring line.
Claim 4
Independent Claim
89 words
A method of fabricating a semiconductor device, comprising the steps of: forming a multi-layer structure on a substrate, the multi-layer structure including a collector layer, a base layer, an emitter layer, and a collector contact layer, the emitter layer being made of material having a forbidden band gap wider than a forbidden band gap of material for the base layer; forming a first capacitor electrode from a portion of the collector contact layer; and forming wiring lines which include a second capacitor electrode opposed to the first capacitor electrode.
Claim 5
Independent Claim
89 words
A method of fabricating a semiconductor device, comprising the steps of: forming a multi-layer structure on a substrate, the multi-layer structure including a collector layer, a base layer, an emitter layer, and a collector contact layer, the emitter layer being made of material having a forbidden band gap wider than a forbidden band gap of material for the base layer; forming a first capacitor electrode from a portion of the collector contact layer; and forming wiring lines which include a second capacitor electrode opposed to the first capacitor electrode.
Claim 6
Dependent Claim
88 words
The method of claim 3, wherein said step of forming wiring-lines comprises simultaneously forming a first wiring line, electrically connected to the emitter layer and including the second capacitor electrode, and a second wiring line, including a capacitor-electrode connecting line, and further comprising the step of simultaneously forming a third wiring line, including a third capacitor electrode opposed to the second capacitor electrode and electrically connected to the first capacitor electrode via the capacitor-electrode connecting line, and a fourth wiring line, electrically connected to the first wiring line.
Claim 7
Independent Claim
68 words
A method of fabricating a semiconductor device, comprising the steps of: forming a heterojunction bipolar transistor including a region; forming a multi-layer capacitor of a laminated structure including three electrodes which contain a capacitor electrode made of a material same as a material for the region of the transistor; simultaneously forming the region of the transistor and the capacitor electrode; and electrically connecting the transistor and the capacitor.
Claim 8
Independent Claim
68 words
A method of fabricating a semiconductor device, comprising the steps of: forming a heterojunction bipolar transistor including a region; forming a multi-layer capacitor of a laminated structure including three electrodes which contain a capacitor electrode made of a material same as a material for the region of the transistor; simultaneously forming the region of the transistor and the capacitor electrode; and electrically connecting the transistor and the capacitor.
Claim 9
Independent Claim
125 words
A method of fabricating a semiconductor device, comprising the steps of: forming a multi-layer structure on a substrate, the multi-layer structure including a collector layer, a base layer, and an emitter layer, the emitter layer being made of material having a forbidden band gap wider than a forbidden band gap of material for the base layer; exposing a portion of the base layer; simultaneously forming an emitter electrode and a first capacitor electrode, the emitter electrode being electrically connected to the emitter layer and having an upper surface in a height position approximately equal to a height position of a surface of the exposed portion of the base layer; and forming wiring lines which include a second capacitor electrode opposed to the first capacitor electrode.
Claim 10
Independent Claim
125 words
A method of fabricating a semiconductor device, comprising the steps of: forming a multi-layer structure on a substrate, the multi-layer structure including a collector layer, a base layer, and an emitter layer, the emitter layer being made of material having a forbidden band gap wider than a forbidden band gap of material for the base layer; exposing a portion of the base layer; simultaneously forming an emitter electrode and a first capacitor electrode, the emitter electrode being electrically connected to the emitter layer and having an upper surface in a height position approximately equal to a height position of a surface of the exposed portion of the base layer; and forming wiring lines which include a second capacitor electrode opposed to the first capacitor electrode.
Claim 11
Independent Claim
89 words
A method of fabricating a semiconductor device, comprising the steps of: forming a multi-layer structure on a substrate, the multi-layer structure including a collector layer, a base layer, an emitter layer, and an emitter contact layer, the emitter layer being made of material having a forbidden band gap wider than a forbidden band gap of material for the base layer; forming a first capacitor electrode from a portion of the emitter contact layer; and forming wiring lines which include a second capacitor electrode opposed to the first capacitor electrode.
Claim 12
Independent Claim
89 words
A method of fabricating a semiconductor device, comprising the steps of: forming a multi-layer structure on a substrate, the multi-layer structure including a collector layer, a base layer, an emitter layer, and an emitter contact layer, the emitter layer being made of material having a forbidden band gap wider than a forbidden band gap of material for the base layer; forming a first capacitor electrode from a portion of the emitter contact layer; and forming wiring lines which include a second capacitor electrode opposed to the first capacitor electrode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-24 | 1998-10-24 | 1999-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-24 | 2002-10-24 | 2003-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-24 | 2006-10-24 | 2007-04-25 | $7700.00 | Window Closed / Lapsed |