Single transistor EEPROM architecture

Claim 2

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being coupled to the bit line, and the second current terminal of the last memory cell in the string being coupled to the reference voltage point; and a decoder having an address input and a plurality of outputs respectively connected to the control terminals of the memory cells for applying, in response to a memory address on the address input during a program mode, a first voltage to the control terminal of at least a first addressed one of the memory cells in the string and a second voltage to the control terminals of a first subset of memory cells comprising any of the memory cells in the string intervening between the addressed memory cell and the bit line, the second voltage being such as to support conduction in the memory cells of the first subset, and the first voltage being such, relative to a program voltage on the bit line, as to support setting the conduction threshold in the first addressed memory cell without supporting conduction therein.

Claim 3

A memory as in claim 1, wherein each of the memory cells is an n-type electrically erasable programmable read only memory ("EEPROM") device, the conduction threshold is a low voltage threshold, and the first voltage is negative relative to the program voltage.

Claim 4

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells disposed in a semiconductor substrate, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being coupled to the bit line, and the second current terminal of the last memory cell in the string being coupled to the reference voltage point; and a decoder having an address input and a plurality of outputs respectively coupled to the control terminals of the memory cells for applying, in response to a memory address on the address input during a conduction threshold set mode, a first voltage to the control terminal of an addressed one of the memory cells in the string, and second voltage(s) to the control terminal(s) respectively of a first subset of memory cell(s) comprising any of the memory cells in the string intervening between the addressed memory cell and the bit line, the second voltage(s) being such as to support conduction in the memory cells of the first subset, and the first voltage being such as to support. setting the conduction threshold in the addressed memory cell to a particular conduction threshold in accordance with a third voltage on the bit line; wherein the substrate is a settable potential substrate for receiving a substrate potential during the conduction threshold set mode so that the absolute values of the first and third voltages relative to ground potential are less that the absolute value of the difference between the first and third voltages.

Claim 5

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells disposed in a semiconductor substrate, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being coupled to the bit line, and the second current terminal of the last memory cell in the string being coupled to the reference voltage point; and a decoder having an address input and a plurality of outputs respectively coupled to the control terminals of the memory cells for applying, in response to a memory address on the address input during a conduction threshold set mode, a first voltage to the control terminal of an addressed one of the memory cells in the string, and second voltage(s) to the control terminal(s) respectively of a first subset of memory cell(s) comprising any of the memory cells in the string intervening between the addressed memory cell and the bit line, the second voltage(s) being such as to support conduction in the memory cells of the first subset, and the first voltage being such as to support. setting the conduction threshold in the addressed memory cell to a particular conduction threshold in accordance with a third voltage on the bit line; wherein the substrate is a settable potential substrate for receiving a substrate potential during the conduction threshold set mode so that the absolute values of the first and third voltages relative to ground potential are less that the absolute value of the difference between the first and third voltages.

Claim 6

A memory as in claim 1 wherein each of the memory cells is an n-type electrically erasable programmable read only memory ("EEPROM") device implemented on a semiconductor substrate, the control terminal being a control gate, the first current terminal being a drain, and the second current terminal being a source.

Claim 7

A memory as in claim 4 wherein within the string, adjacent EEPROM devices are connected source-to-source and drain-to-drain, alternately.

Claim 8

A memory as in claim 4 wherein within the string, adjacent EEPROM devices are connected source-to-drain, the drain of the first memory cell in the string being coupled to the bit line, and the source of the last memory cell in the string being coupled to the reference voltage point.

Claim 9

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being directly connected to the bit line, and the second current terminal of the last memory cell in the string being directly connected to the reference voltage point; and a decoder having an address input and a plurality of outputs respectively connected to the control terminals of the memory cells for applying, in response to a memory address on the address input during a conduction threshold set mode, a first voltage to the control terminal of at least a first addressed one of the memory cells in the string and a second voltage to the control terminals of a first subset of memory cells comprising the memory cells in the string intervening between the addressed memory cell and the bit line, the second voltage being such as to support conduction in the memory cells of the first subset, and the first voltage being such, relative to a voltage on the bit line, as to support setting the conduction threshold in the first addressed memory cell without supporting conduction therein.

Claim 10

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being directly connected to the bit line, and the second current terminal of the last memory cell in the string being directly connected to the reference voltage point; and a decoder having an address input and a plurality of outputs respectively connected to the control terminals of the memory cells for applying, in response to a memory address on the address input during a conduction threshold set mode, a first voltage to the control terminal of at least a first addressed one of the memory cells in the string and a second voltage to the control terminals of a first subset of memory cells comprising the memory cells in the string intervening between the addressed memory cell and the bit line, the second voltage being such as to support conduction in the memory cells of the first subset, and the first voltage being such, relative to a voltage on the bit line, as to support setting the conduction threshold in the first addressed memory cell without supporting conduction therein.

Claim 11

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being coupled to the bit line, and the second current terminal of the last memory cell in the string being coupled to the reference voltage point; and a decoder having an address input and a plurality of outputs respectively coupled to the control terminals of the memory cells for applying, in response to a memory address on the address input during a conduction threshold set mode, a first voltage to the control terminal of an addressed one of the memory cells in the string, second voltage(s) to the control terminal(s) respectively of a first subset of memory cell(s) comprising any of the memory cells in the string intervening between the addressed memory cell and the bit line, and third voltage(s) to the control terminal(s) respectively of a second subset of memory cell(s) comprising any of the memory cells in the string intervening between the addressed memory cell and the bit line, the second and third voltage(s) being such as to support conduction in the memory cells of the first and second subsets, and the first voltage and the reference voltage being such as to support setting the conduction threshold in the first addressed memory cell to a particular conduction threshold.

Claim 12

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being coupled to the bit line, and the second current terminal of the last memory cell in the string being coupled to the reference voltage point; and a decoder having an address input and a plurality of outputs respectively coupled to the control terminals of the memory cells for applying, in response to a memory address on the address input during a conduction threshold set mode, a first voltage to the control terminal of an addressed one of the memory cells in the string, second voltage(s) to the control terminal(s) respectively of a first subset of memory cell(s) comprising any of the memory cells in the string intervening between the addressed memory cell and the bit line, and third voltage(s) to the control terminal(s) respectively of a second subset of memory cell(s) comprising any of the memory cells in the string intervening between the addressed memory cell and the bit line, the second and third voltage(s) being such as to support conduction in the memory cells of the first and second subsets, and the first voltage and the reference voltage being such as to support setting the conduction threshold in the first addressed memory cell to a particular conduction threshold.

Claim 13

A memory as in claim 3 wherein each of the memory cells is an n-type electrically erasable programmable read only memory ("EEPROM") device implemented on a semiconductor substrate, the control terminal being a control gate, the first current terminal being a drain, and the second current terminal being a source.

Claim 14

A memory as in claim 7, wherein the conduction threshold is a high voltage threshold, and the first voltage is positive relative to the bit line voltage.

Claim 15

A memory as in claim 7, wherein the conduction threshold is a low voltage threshold, and the first voltage is negative relative to the bit line voltage.

Claim 16

A memory as in claim 7, wherein the outputs of the decoder are further for applying, in response to a memory address on the address input during a read mode, a third voltage to the control terminal of a second addressed one of the memory cells in the string and fourth voltages to the control terminals of a second subset of the memory cells intervening in the string between the second addressed memory cell and the bit line, and between the second addressed memory cell and the reference voltage point, the fourth voltage being such as to support conduction in the memory cells of the second subset, and the third voltage being such as to support sensing the conduction threshold in the second addressed memory cell.

Claim 17

A memory as in claim 11 wherein: the memory cells are field effect devices fabricated in a semiconductor substrate, each having a control gate coupled to the control terminals, a floating gate, and a channel region in the substrate between a source and a drain, under electrostatic control of the control gate and the floating gate; and wherein a substrate potential is applied to the substrate.

Claim 18

A memory as in claim 13 wherein the substrate potential is a ground potential.

Claim 19

A memory as in claim 13, wherein the substrate potential is variable so that the absolute values of the first and third voltages relative to ground potential are less that the absolute value of the difference between the first and third voltages.

Claim 20

A memory as in claim 7 wherein each of the memory cells is an n-type electrically erasable programmable read only memory ("EEPROM") device implemented on a semiconductor substrate, the control terminal being a control gate, the first current terminal being a drain, and the second current terminal being a source.

Claim 21

A memory as in claim 16 wherein within the string, adjacent EEPROM devices are connected source-to-source and drain-to-drain, alternately.

Claim 22

A memory as in claim 16 wherein within the string, adjacent EEPROM devices are connected source-to-drain, the drain of the first memory cell in the string being directly connected to the bit line, and the source of the last memory cell in the string being connected to the reference voltage point.

Claim 23

A memory as in claim 16 wherein the outputs of the decoder are further for applying, during an erase mode, a fourth voltage to the substrate and fifth voltages to the control gates of the memory cells, the fifth voltage being positive relative to the fourth voltage and of a magnitude to support tunneling in an EEPROM device.

Claim 24

A memory as in claim 19 wherein the outputs of the decoder are further for applying, during an erase mode, a sixth voltage to the bit line and a seventh voltage to the reference point, the sixth and seventh voltages being non-negative relative to the fourth voltage to prevent leakage.

Claim 27

A method as in claim 21 wherein the memory cells are electrically erasable programmable read-only memory ("EEPROM") cells disposed in a semiconductor substrate, further comprising applying a potential to the substrate so that the absolute values of the first and second voltages relative to ground potential are less that the absolute value of the difference between the first and third voltages.

Claim 28

A NAND array of memory cells coupled to a bit line and having respective settable voltage thresholds, comprising: means for erasing the memory cells in the NAND array to set the respective voltage thresholds thereof at a high threshold indicative of a first logical state; means for selecting one of the memory cells for programming; means for applying a first voltage to the bit line, the first voltage having a value dependent on a logical state for programming the selected memory cell; means for applying a second voltage to the selected memory cell; means for applying, when any of the memory cells intervene between the selected memory cell and the bit line, a third voltage to the intervening memory cell(s), the third voltage being such as to support conduction in the intervening memory cells of the first subset without disturbing the voltage thresholds thereof, the second voltage being such, relative to the first voltage, as to set the voltage threshold of the selected memory cell to a low voltage threshold when the first voltage is indicative of a second logical state which is a complement of the first logical state, and not disturb the voltage threshold of the selected memory cell when the first voltage is indicative of the first logical state.

Claim 29

A NAND array of memory cells coupled to a bit line and having respective settable voltage thresholds, comprising: means for erasing the memory cells in the NAND array to set the respective voltage thresholds thereof at a high threshold indicative of a first logical state; means for selecting one of the memory cells for programming; means for applying a first voltage to the bit line, the first voltage having a value dependent on a logical state for programming the selected memory cell; means for applying a second voltage to the selected memory cell; means for applying, when any of the memory cells intervene between the selected memory cell and the bit line, a third voltage to the intervening memory cell(s), the third voltage being such as to support conduction in the intervening memory cells of the first subset without disturbing the voltage thresholds thereof, the second voltage being such, relative to the first voltage, as to set the voltage threshold of the selected memory cell to a low voltage threshold when the first voltage is indicative of a second logical state which is a complement of the first logical state, and not disturb the voltage threshold of the selected memory cell when the first voltage is indicative of the first logical state.

Claim 30

A NAND array as in claim 23 wherein the memory cells are electrically erasable programmable read-only memory ("EEPROM") cells disposed in a semiconductor substrate, further comprising means for applying a potential to the substrate so that the absolute values of the first and second voltages relative to ground potential are less that the absolute value of the difference between the first and third voltages.