Programmable interconnect architecture using fewer storage cells than switches

Claim 2

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; an I×J array of N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where I, J and N are integers and I+J is greater than 2 , each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, and wherein the state of each control signal is a function of the state of the M inputs of said decoder.

Claim 3

The user re-programmable interconnect architecture of claim 1 wherein a selected state of the M inputs of said decoder causes each control signal from said decoder to assume said off state.

Claim 4

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; N user re-programmable interconnect elements connected between different selected Ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal: M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, wherein the state of each control signal is a function of the state of the M inputs of said decoder, a selected state of the M inputs of said decoder means causes each control signal from said decoder to assume said off state, and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder comprises a one of N decoder circuit.

Claim 5

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; N user re-programmable interconnect elements connected between different selected Ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal: M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, wherein the state of each control signal is a function of the state of the M inputs of said decoder, a selected state of the M inputs of said decoder means causes each control signal from said decoder to assume said off state, and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder comprises a one of N decoder circuit.

Claim 6

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, wherein the state of each control signal is a function of the state of the M inputs of said decoder, a selected state of the M inputs of said decoder means causes each control signal from said decoder to assume said off state, and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder comprises a two-bit decoder circuit.

Claim 7

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, wherein the state of each control signal is a function of the state of the M inputs of said decoder, a selected state of the M inputs of said decoder means causes each control signal from said decoder to assume said off state, and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder comprises a two-bit decoder circuit.

Claim 8

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, wherein the state of each control signal is a function of the state of the M inputs of said decoder, a selected state of the M inputs of said decoder means causes each control signal from said decoder to assume said off state, and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder comprises a more than two-bit decoder circuit.

Claim 9

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, wherein the state of each control signal is a function of the state of the M inputs of said decoder, a selected state of the M inputs of said decoder means causes each control signal from said decoder to assume said off state, and wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder comprises a more than two-bit decoder circuit.

Claim 10

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a decoded/driver for decoding input signals associated with each of said user re-programmable interconnect elements, each of said decoder/drivers having a first input, a second input and an output, said output connected to a single associated user re-programmable interconnect element, for driving said single associated user re-programmable interconnect element in response to signals at said first and second inputs; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer, the output of each of said first active storage elements connected to the first inputs of a different subset of said decoder/drivers; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer, the output of each of said second active storage elements connected to the second inputs of a different subset of said decoder/drivers such that the first and second inputs of each of said decoder/drivers are connected to the outputs of one each of said first and second active storage elements; and wherein each of said decoder/drivers will switch said single associated user re-programmable interconnect element to its on state in response to said selected state outputs appearing at both its first and second inputs, and wherein M 1 +M 2 <N.

Claim 11

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a decoded/driver for decoding input signals associated with each of said user re-programmable interconnect elements, each of said decoder/drivers having a first input, a second input and an output, said output connected to a single associated user re-programmable interconnect element, for driving said single associated user re-programmable interconnect element in response to signals at said first and second inputs; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer, the output of each of said first active storage elements connected to the first inputs of a different subset of said decoder/drivers; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer, the output of each of said second active storage elements connected to the second inputs of a different subset of said decoder/drivers such that the first and second inputs of each of said decoder/drivers are connected to the outputs of one each of said first and second active storage elements; and wherein each of said decoder/drivers will switch said single associated user re-programmable interconnect element to its on state in response to said selected state outputs appearing at both its first and second inputs, and wherein M 1 +M 2 <N.

Claim 12

The user re-programmable interconnect architecture of claim 6 wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder/drivers comprise ANDing circuits.

Claim 13

The user re-programmable interconnect architecture of claim 6 wherein said decoder/drivers comprises: a first group of decoder lines each one of which is connected to one of the outputs of said first active storage elements; a second group of decoder lines each one of which is connected to one of the outputs of said second active storage elements.

Claim 14

The user re-programmable interconnect architecture of claim 8 wherein said first group and said second group of decoder lines are single line decoder lines.

Claim 15

The user re-programmable interconnect architecture of claim 9 wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder/drivers comprise ANDing circuits.

Claim 16

The user re-programmable interconnect architecture of claim 8 wherein said first group of decoder lines are in non-parallel relationship with said interconnect conductors.

Claim 17

The user re-programmable interconnect architecture of claim 10 wherein said first group of decoder lines are in non-parallel relationship with said interconnect conductors.

Claim 18

The user re-programmable interconnect architecture of claim 8 wherein both said first group of decoder lines and said second group of decoder lines are in non-parallel relationship with said interconnect conductors.

Claim 19

The user re-programmable interconnect architecture of claim 10 wherein both said first group of decoder lines and said second group of decoder lines are in non-parallel relationship with said interconnect conductors.

Claim 20

The user re-programmable interconnect architecture of claim 6 wherein said group of interconnect conductors comprises a first subgroup of K 1 interconnect conductors and a second subgroup of K 2 interconnect conductors and wherein said first subgroup and said second subgroup of interconnect conductors intersect at K predetermined locations, and wherein K, K 1 , and K 2 are all integers, and wherein the user re-programmable interconnect architecture is partially depopulated so that N is an integer in the range of about 25% of K to about 75% of K.

Claim 21

The user re-programmable interconnect architecture of claim 15 wherein said decoder/drivers comprise: a first group of decoder lines each one of which is connected to one of the outputs of said first active storage elements; a second group of decoder lines each one of which is connected to one of the outputs of said second active storage elements.

Claim 22

The user re-programmable interconnect architecture of claim 16 wherein said first group of decoder lines are in non-parallel relationship with said interconnect conductors.

Claim 23

The user re-programmable interconnect architecture of claim 17 wherein said first group and said second group of decoder lines are single line decoder lines.

Claim 24

The user re-programmable interconnect architecture of claim 16 wherein both said first group of decoder lines and said second group of decoder lines are in non-parallel relationship with said interconnect conductors.

Claim 25

The user re-programmable interconnect architecture of claim 19 wherein said active storage elements comprise SRAM cells, said user re-programmable interconnect elements comprise MOS transistors, and said decoder/drivers comprise ANDing circuits.

Claim 26

The user re-programmable interconnect architecture of claim 20 wherein said first group and said second group of decoder lines are single line decoder lines.

Claim 27

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer; a first decoder having M 1 inputs connected to outputs of said first active storage elements and having a plurality of outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements in a first subgroup thereof, wherein the state of each control signal is a function of the state of the M 1 inputs of said first decoder; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer; and a second decoder having M 1 inputs connected to outputs of said active storage elements and having a plurality of outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements in a second subgroup thereof, wherein the state of each control signal is a function of the state of the M 2 inputs of said second decoder; and wherein M 1 +M 2 <N.

Claim 28

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 first active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 1 is an integer; a first decoder having M 1 inputs connected to outputs of said first active storage elements and having a plurality of outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements in a first subgroup thereof, wherein the state of each control signal is a function of the state of the M 1 inputs of said first decoder; M 2 second active storage elements, each having a first unselected state and a second selected state available at an output thereof, where M 2 is an integer; and a second decoder having M 1 inputs connected to outputs of said active storage elements and having a plurality of outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements in a second subgroup thereof, wherein the state of each control signal is a function of the state of the M 2 inputs of said second decoder; and wherein M 1 +M 2 <N.

Claim 29

The user re-programmable interconnect architecture of claim 22 wherein: said first decoder comprises a first set of decoder lines and said second decoder comprises a second set of decoder lines; and said first set of decoder lines and said second set of decoder lines are comprised of single line decoder lines.

Claim 30

The user re-programmable interconnect architecture of claim 23 wherein: at least one element of said first set of decoder lines and said group of interconnect conductors are in non-parallel relationship with each other.

Claim 31

The user re-programmable interconnect architecture of claim 24 wherein: a plurality of the elements of said first set of decoder lines are in non-parallel relationship with said group of interconnect conductors.

Claim 32

The user re-programmable interconnect architecture of claim 25 wherein: a plurality of the elements of said first set of decoder lines and a plurality of the elements of said second set of decoder lines are in non-parallel relationship with said group of interconnect conductors.

Claim 33

The user re-programmable interconnect architecture of claim 26 wherein: substantially all of the elements of said first set of decoder lines and substantially all of the elements of said second set of decoder lines are in non-parallel relationship with said group of interconnect conductors.

Claim 34

The user re-programmable interconnect architecture of claim 27 wherein said group of interconnect conductors comprises a first subgroup of K 1 interconnect conductors and a second subgroup of K 2 interconnect conductors wherein said first subgroup and said. Second subgroup of interconnect conductors intersect at K predetermined locations, and wherein K, K 1 , and K 2 are all integers, and wherein the user re-programmable interconnect architecture is partially depopulated so that N is an integer in the range of about 25% of K to about 75% of K.

Claim 35

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements having a first control input and a second control input, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of an internally-generated control signal; M 1 first active storage elements, each having a first unselected state and a second selected state and an output, where M 1 is an integer, the output of each first active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a first control input of each of a first group of said user re-programmable interconnect elements; M 2 second active storage elements, each having a first unselected state and a second selected state and an output, where M 2 is an integer, the output of each second active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a second control input of a second group of said user re-programmable interconnect elements such that each of said user re-programmable interconnect elements is connected to an output from one of said first and one of said second active storage elements; a control-signal generator, in each of said user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the first and second active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 36

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors comprising a group of interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors in said group, where N is an integer, each of said user re-programmable interconnect elements having a first control input and a second control input, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of an internally-generated control signal; M 1 first active storage elements, each having a first unselected state and a second selected state and an output, where M 1 is an integer, the output of each first active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a first control input of each of a first group of said user re-programmable interconnect elements; M 2 second active storage elements, each having a first unselected state and a second selected state and an output, where M 2 is an integer, the output of each second active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to a second control input of a second group of said user re-programmable interconnect elements such that each of said user re-programmable interconnect elements is connected to an output from one of said first and one of said second active storage elements; a control-signal generator, in each of said user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the first and second active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 37

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: an input/output pad; a first input/output pad conductor extending in a first direction from said input output pad; a second input/output pad conductor extending in a second direction from said input/output pad, said second direction substantially different from said first direction; a plurality of first interconnect conductors insulated from and intersecting said first input/output pad conductor; a plurality of second interconnect conductors insulated from and intersecting said second input/output pad conductor, said second interconnect conductors insulated from and forming intersections with said first interconnect conductors; a plurality of first user re-programmable interconnect elements, one of said first user re-programmable interconnect elements connected between each of said first interconnect conductors and said first input/output pad conductor, each of said first user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a first plurality of active storage elements, each one of said first plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of first user re-programmable interconnect elements in response to its state; a plurality of second user re-programmable interconnect elements, one of said second user re-programmable interconnect elements connected between each of said second interconnect conductors and said second input/output pad conductor, each of said second user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a second plurality of active storage elements, each one of said second plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of second user re-programmable interconnect elements in response to its state; N third user re-programmable interconnect elements, where N is an integer, one of said third user re-programmable interconnect elements connected at selected ones of said intersections between said first and second interconnect conductors, each of said third user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 third active storage elements, each having an output and having a first unselected state and a second selected state, where M 1 is an integer, the output of each third active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one first control input of each of a first group of said third user re-programmable interconnect elements; M 2 fourth active storage elements, each having an output and a first unselected state and a second selected state, where M 2 is an integer, the output of each fourth active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one second control input of a second group of said third user re-programmable interconnect elements, said first group and said second group chosen such that each of said user re-programmable interconnect elements is connected to an output from one of said third and one of said fourth active storage elements; a control-signal generator, in each of said third user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the third and fourth active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 38

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: an input/output pad; a first input/output pad conductor extending in a first direction from said input output pad; a second input/output pad conductor extending in a second direction from said input/output pad, said second direction substantially different from said first direction; a plurality of first interconnect conductors insulated from and intersecting said first input/output pad conductor; a plurality of second interconnect conductors insulated from and intersecting said second input/output pad conductor, said second interconnect conductors insulated from and forming intersections with said first interconnect conductors; a plurality of first user re-programmable interconnect elements, one of said first user re-programmable interconnect elements connected between each of said first interconnect conductors and said first input/output pad conductor, each of said first user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a first plurality of active storage elements, each one of said first plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of first user re-programmable interconnect elements in response to its state; a plurality of second user re-programmable interconnect elements, one of said second user re-programmable interconnect elements connected between each of said second interconnect conductors and said second input/output pad conductor, each of said second user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a second plurality of active storage elements, each one of said second plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of second user re-programmable interconnect elements in response to its state; N third user re-programmable interconnect elements, where N is an integer, one of said third user re-programmable interconnect elements connected at selected ones of said intersections between said first and second interconnect conductors, each of said third user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 third active storage elements, each having an output and having a first unselected state and a second selected state, where M 1 is an integer, the output of each third active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one first control input of each of a first group of said third user re-programmable interconnect elements; M 2 fourth active storage elements, each having an output and a first unselected state and a second selected state, where M 2 is an integer, the output of each fourth active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one second control input of a second group of said third user re-programmable interconnect elements, said first group and said second group chosen such that each of said user re-programmable interconnect elements is connected to an output from one of said third and one of said fourth active storage elements; a control-signal generator, in each of said third user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the third and fourth active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 39

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: a plurality of I/O structures arranged in an array of rows and columns, each of said I/O structures comprising an I/O pad, a first input/output pad conductor extending in a first direction from said input output pad and a second input/output pad conductor extending in a second direction from said input/output pad, said second direction substantially different from said first direction; a row group of first interconnect conductors in each row of said array, each of said first interconnect conductors in each row group insulated from and intersecting said first input/output pad conductors of each of said I/O structures in their row; a column group of second interconnect conductors in each column of said array, each of said second interconnect conductors in each column group insulated from and intersecting said second input/output pad conductors of each of said I/O structures in their column, said second interconnect conductors insulated from and forming intersections with said first interconnect conductors in each row group thereof; a plurality of first user re-programmable interconnect elements, one of said first user re-programmable interconnect elements connected between each of said first interconnect conductors and said first input/output pad conductors at intersections thereof, each of said first user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a first plurality of active storage elements, each one of said first plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of first user re-programmable interconnect elements in response to its state; a plurality of second user re-programmable interconnect elements, one of said second user re-programmable interconnect elements connected between each of said second interconnect conductors and said second input/output pad conductors at intersections thereof, each of said second user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a second plurality of active storage elements, each one of said second plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of second user re-programmable interconnect elements in response to its state; N third user re-programmable interconnect elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, where N is an integer, one of said third user re-programmable interconnect elements connected at selected ones of said intersections between said first and second interconnect conductors, each of said third user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 third active storage elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, each having an output and having a first unselected state and a second selected state, where M 1 is an integer, the output of each third active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one first control input of each of a first group of said third user re-programmable interconnect elements in its I/O structure; M 2 fourth active storage elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, each having an output and a first unselected state and a second selected state, where M 2 is an integer, the output of each fourth active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one second control input of a second group of said third user re-programmable interconnect elements in its I/O structure, said first group and said second group chosen such that each of said user re-programmable interconnect elements is connected to an output from one of said third and one of said fourth active storage elements; a control-signal generator, in each of said third user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the third and fourth active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 40

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: a plurality of I/O structures arranged in an array of rows and columns, each of said I/O structures comprising an I/O pad, a first input/output pad conductor extending in a first direction from said input output pad and a second input/output pad conductor extending in a second direction from said input/output pad, said second direction substantially different from said first direction; a row group of first interconnect conductors in each row of said array, each of said first interconnect conductors in each row group insulated from and intersecting said first input/output pad conductors of each of said I/O structures in their row; a column group of second interconnect conductors in each column of said array, each of said second interconnect conductors in each column group insulated from and intersecting said second input/output pad conductors of each of said I/O structures in their column, said second interconnect conductors insulated from and forming intersections with said first interconnect conductors in each row group thereof; a plurality of first user re-programmable interconnect elements, one of said first user re-programmable interconnect elements connected between each of said first interconnect conductors and said first input/output pad conductors at intersections thereof, each of said first user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a first plurality of active storage elements, each one of said first plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of first user re-programmable interconnect elements in response to its state; a plurality of second user re-programmable interconnect elements, one of said second user re-programmable interconnect elements connected between each of said second interconnect conductors and said second input/output pad conductors at intersections thereof, each of said second user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; a second plurality of active storage elements, each one of said second plurality of active storage elements having a first unselected state and a second selected state and providing said control signal to a different one of said plurality of second user re-programmable interconnect elements in response to its state; N third user re-programmable interconnect elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, where N is an integer, one of said third user re-programmable interconnect elements connected at selected ones of said intersections between said first and second interconnect conductors, each of said third user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M 1 third active storage elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, each having an output and having a first unselected state and a second selected state, where M 1 is an integer, the output of each third active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one first control input of each of a first group of said third user re-programmable interconnect elements in its I/O structure; M 2 fourth active storage elements associated with each intersecting row group and column group of interconnect conductors in each I/O structure, each having an output and a first unselected state and a second selected state, where M 2 is an integer, the output of each fourth active storage element providing an off output signal if said storage element is in its unselected state and an on signal if said storage element is in its selected state, each of said outputs connected to at least one second control input of a second group of said third user re-programmable interconnect elements in its I/O structure, said first group and said second group chosen such that each of said user re-programmable interconnect elements is connected to an output from one of said third and one of said fourth active storage elements; a control-signal generator, in each of said third user re-programmable interconnect elements, for generating said control signal to place it in its on state in response to the presence of on output signals from the third and fourth active storage elements to which it is connected; and wherein M 1 +M 2 <N.

Claim 41

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: a plurality of interconnect conductors; a plurality of N switching elements organized into a plurality of switching matrices, wherein each switching element is capable of being switched between an on state and an off state, and each switching element is capable of shorting at least two of said interconnect conductors when it is in said on state; at least K intersections formed by said interconnect conductors; N Q-input decoders wherein Q is an integer greater than 1, one of said N Q-input decoders associated with each N switching elements; an output of each of said Q-input decoders connected to and controlling the state of its associated N switching elements; Q sets of decoder lines, each decoder line driven by a storage element wherein one decoder line from each of said Q sets of decoder lines is connected to one of the inputs of each said Q-bit decoder.

Claim 42

A user re-programmable interconnect architecture disposed on a microcircuit substrate comprising: a plurality of interconnect conductors; a plurality of N switching elements organized into a plurality of switching matrices, wherein each switching element is capable of being switched between an on state and an off state, and each switching element is capable of shorting at least two of said interconnect conductors when it is in said on state; at least K intersections formed by said interconnect conductors; N Q-input decoders wherein Q is an integer greater than 1, one of said N Q-input decoders associated with each N switching elements; an output of each of said Q-input decoders connected to and controlling the state of its associated N switching elements; Q sets of decoder lines, each decoder line driven by a storage element wherein one decoder line from each of said Q sets of decoder lines is connected to one of the inputs of each said Q-bit decoder.

Claim 43

The user re-programmable interconnect device of claim 32 wherein: at least one of said Q sets of decoder lines is in non-parallel relationship to said interconnect conductors.

Claim 44

The user re-programmable interconnect device of claim 32 wherein: at least two of said Q sets of decoder lines are in non-parallel relationship to said interconnect conductors.

Claim 45

The user re-programmable interconnect device of claim 32 wherein: Q of said Q sets of decoder lines are in non-parallel relationship to said interconnect conductors.

Claim 46

The user re-programmable interconnect device of claim 32 wherein: at least one of said switching matrices is partially depopulated so that 25%K≦N≦75%K.

Claim 47

A user re-programmable interconnect architecture according to claim 32 wherein Q>3.

Claim 48

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; an I×J array of N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where I, J and N are integers and I and J are greater than one, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, and wherein the state of each control signal is a function of the state of the M inputs of said decoder.

Claim 49

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; an I×J array of N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where I, J and N are integers and I and J are greater than one, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, and wherein the state of each control signal is a function of the state of the M inputs of said decoder.

Claim 50

A user re-programmable interconnect architecture comprising: a plurality of non-converging interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; decoder means having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, and wherein the state of each control signal is a function of the state of the M inputs of said decoder means.

Claim 51

A user re-programmable interconnect architecture comprising: a plurality of non-converging interconnect conductors; N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where N is an integer, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; decoder means having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, and wherein the state of each control signal is a function of the state of the M inputs of said decoder means.

Claim 52

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; an I×J array of N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where I, J and N are integers and I and J are greater than one, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs simultaneously providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, and wherein the state of each control signal is a function of the state of the M inputs of said decoder.

Claim 53

A user re-programmable interconnect architecture comprising: a plurality of interconnect conductors; an I×J array of N user re-programmable interconnect elements connected between different selected ones of said plurality of interconnect conductors, where I, J and N are integers and I and J are greater than one, each of said user re-programmable interconnect elements being switchable between an on state and an off state in response to the state of a control signal; M active storage elements, each having a first unselected state and a second selected state, where M is an integer and M<N; a decoder having M inputs connected to outputs of said active storage elements and having N outputs, each of said outputs simultaneously providing a control signal to one of said N user re-programmable interconnect elements, said control signal having an on state and an off state, and wherein the state of each control signal is a function of the state of the M inputs of said decoder.