US4771284A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic array with programmable element output generation
Assignee: International Business Machines Corp
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Filing: 1986-08-13
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Granted: 1988-09-13
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Expires: 2006-08-13
Abstract
Abstract A programmable logic array having a plurality of electrically isolated input lines connected to an input circuit for providing an input signal to one of the plurality of input lines. Also included are a plurality of electrically isolated output lines positioned relative to the input lines to form an array having a plurality of non-conductive intersections. A plurality of programmable circuits, each positioned at a selected one of the intersections and interconnecting an adjacent input line, an adjacent output line and one of two output potentials that define one of two output states are provided. The programmable circuit is further connected to the input line such that when an input signal is received on the input line, the selected output potential representing one of the two output states is provided on the output line.
Inventors
- 👤 Robert P. Masleid
- 👤 Martin S. Schmookler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
175 words
A programmable logic array comprising: a plurality of parallel positioned electrically isolated input lines; input means for providing an input signal on one of said input lines; a plurality of parallel positioned electrically isolated output lines collectively positioned orthogonally relative to said input lines forming an array having a plurality of nonconductive intersections of said input lines and said output lines, each intersection including an adjacent input line and an output line; and a plurality of programmable means, each positioned at each of said intersections and interconnecting said adjacent input line and output line, said programmable means further connectable to either a first voltage potential or said adjacent input line for providing a programmed output signal of either the first voltage potential or the input signal present on the connected adjacent input line to the connected adjacent output line to define one of two output states when said input signal is received from said connected input line wherein an output potential for either of the two output states is provided only through the progammable means.
Claim 2
Dependent Claim
175 words
A programmable logic array comprising: a plurality of parallel positioned electrically isolated input lines; input means for providing an input signal on one of said input lines; a plurality of parallel positioned electrically isolated output lines collectively positioned orthogonally relative to said input lines forming an array having a plurality of nonconductive intersections of said input lines and said output lines, each intersection including an adjacent input line and an output line; and a plurality of programmable means, each positioned at each of said intersections and interconnecting said adjacent input line and output line, said programmable means further connectable to either a first voltage potential or said adjacent input line for providing a programmed output signal of either the first voltage potential or the input signal present on the connected adjacent input line to the connected adjacent output line to define one of two output states when said input signal is received from said connected input line wherein an output potential for either of the two output states is provided only through the progammable means.
Claim 3
Dependent Claim
49 words
A programmable array according to claim 1 wherein said programmable means are transistors having a drain terminal connected to the adjacent output line, a gate terminal connected to the adjacent input line and a source terminal programmable connected to either said first voltage potential or said adjacent input line.
Claim 4
Dependent Claim
16 words
A programmable array according to claim 2 wherein said first voltage potential is a ground potential.
Claim 5
Dependent Claim
21 words
A programmable array according to claim 2 wherein said input means includes an address decoding means for providing said input signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-13 | 1992-03-14 | 1992-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-13 | 1996-03-14 | 1996-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-13 | 2000-03-14 | 2000-09-13 | $7700.00 | Window Closed / Lapsed |