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US5405800A
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Method of fabricating a semiconductor memory device
Assignee: Panasonic Holdings Corp
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Filing: 1994-07-12
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Granted: 1995-04-11
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Expires: 2014-07-12
Abstract
Abstract A method of fabricating a semiconductor memory device on a semiconductor substrate is disclosed. A gate electrode that becomes a word line, a bit line, and a charge-storage electrode are formed in a memory cell array region of a semiconductor substrate. A capacitor insulator layer and a plate electrode are formed in that order. Then, a BPSG film is formed in the memory cell array region and in the peripheral circuit region. A resist pattern is formed on the BPSG film, leaving the memory cell array region exposed. Using the resist pattern thus formed as a mask, an etching treatment is applied to remove an upper surface portion of the BPSG film lying within the memory cell array region by a given amount. After the resist pattern is removed, the BPSG film is heated in order that it reflows to planarize.
Inventors
- 👤 Hisashi Ogawa
- 👤 Susumu Matsumoto
- 👤 Shin Hashimoto
- 👤 Hiroyuki Umimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:46
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
187 words
A method of fabricating a semiconductor memory device, said method comprising: a first step of forming a word line, a bit line, and a charge-storage electrode in a memory cell array region which is formed on a semiconductor substrate; a second step of forming a plate electrode over said charge-storage electrode wherein a capacitor insulator layer is sandwiched between said charge-storage electrode and said plate electrode; a third step of forming an interlayer insulator that flows upon heating on said memory cell array region as well as on a peripheral circuit region which is formed on said semiconductor substrate; a fourth step of forming a resist pattern on said interlayer insulator, leaving said memory cell array region exposed; a fifth step of etching said interlayer insulator using said resist pattern as a mask so as to remove only an upper surface portion of said interlayer insulator within said memory cell array region; and a sixth step of, after removing said resist pattern, subjecting said interlayer insulator on said memory cell array region and peripheral circuit region to a heat treatment in order that said interlayer insulator reflows.
Claim 2
Independent Claim
187 words
A method of fabricating a semiconductor memory device, said method comprising: a first step of forming a word line, a bit line, and a charge-storage electrode in a memory cell array region which is formed on a semiconductor substrate; a second step of forming a plate electrode over said charge-storage electrode wherein a capacitor insulator layer is sandwiched between said charge-storage electrode and said plate electrode; a third step of forming an interlayer insulator that flows upon heating on said memory cell array region as well as on a peripheral circuit region which is formed on said semiconductor substrate; a fourth step of forming a resist pattern on said interlayer insulator, leaving said memory cell array region exposed; a fifth step of etching said interlayer insulator using said resist pattern as a mask so as to remove only an upper surface portion of said interlayer insulator within said memory cell array region; and a sixth step of, after removing said resist pattern, subjecting said interlayer insulator on said memory cell array region and peripheral circuit region to a heat treatment in order that said interlayer insulator reflows.
Claim 3
Dependent Claim
61 words
A method of fabricating a semiconductor memory device as in claim 1, wherein said fourth step includes a step of forming said resist pattern in such a way that said interlayer insulator, which lies in said peripheral circuit region and which is formed at said fifth step, has at the edge thereof a projection that surrounds said memory cell array region.
Claim 4
Dependent Claim
43 words
A method of fabricating a semiconductor memory device as in claim 2, wherein said fourth step includes a step of forming said resist pattern in such a way that said projection is spaced from said memory cell array region at said fifth step.
Claim 5
Dependent Claim
61 words
A method of fabricating a semiconductor memory device as in claim 1, wherein said fourth step includes a step of forming said resist pattern in such a way that said interlayer insulator, which lies in said peripheral circuit region and which is formed at said fifth step, has at the edge thereof a recess that surrounds said memory cell array region.
Claim 6
Dependent Claim
43 words
A method of fabricating a semiconductor memory device as in claim 4, wherein said fourth step includes a step of forming said resist pattern in such a way that said recess is spaced from said memory cell array region at said fifth step.
Claim 7
Independent Claim
168 words
A method of fabricating a semiconductor memory device, said method comprising: a first step of forming a word line, a bit line, and a charge-storage electrode in a memory cell array region which is formed on a semiconductor substrate; a second step of forming a plate electrode over said charge-storage electrode wherein a-capacitor insulator layer is sandwiched between said charge-storage electrode and said plate electrode; a third step of forming a resist pattern on said plate electrode, leaving a peripheral circuit region which is formed on said semiconductor substrate exposed; a fourth step of forming an insulator layer used for a reduction in level difference in said peripheral circuit region using said resist pattern as a mask; a fifth step of, after removing said resist pattern, forming an interlayer insulator that flows upon heating on said memory cell array region as well as on said peripheral circuit region; and a sixth step of subjecting said interlayer insulator to a heat treatment in order that said interlayer insulator reflows.
Claim 8
Independent Claim
168 words
A method of fabricating a semiconductor memory device, said method comprising: a first step of forming a word line, a bit line, and a charge-storage electrode in a memory cell array region which is formed on a semiconductor substrate; a second step of forming a plate electrode over said charge-storage electrode wherein a-capacitor insulator layer is sandwiched between said charge-storage electrode and said plate electrode; a third step of forming a resist pattern on said plate electrode, leaving a peripheral circuit region which is formed on said semiconductor substrate exposed; a fourth step of forming an insulator layer used for a reduction in level difference in said peripheral circuit region using said resist pattern as a mask; a fifth step of, after removing said resist pattern, forming an interlayer insulator that flows upon heating on said memory cell array region as well as on said peripheral circuit region; and a sixth step of subjecting said interlayer insulator to a heat treatment in order that said interlayer insulator reflows.
Claim 9
Dependent Claim
33 words
A method of fabricating a semiconductor memory device as in claim 6, wherein said level difference reduction insulator layer is a silicon dioxide layer formed by means of a liquid phase epitaxy method.
Claim 10
Dependent Claim
61 words
A method of fabricating a semiconductor memory device as in claim 6, wherein said third step includes a step of forming said resist pattern in such a way that said interlayer insulator, which lies in said peripheral circuit region and which is formed at said fifth step, has at the edge thereof a recess that surrounds said memory cell array region.
Claim 11
Independent Claim
215 words
A method of fabricating a semiconductor memory device, said method comprising: a first step of forming a word line, a bit line, and a charge-storage electrode in a memory cell array region which is formed on a semiconductor substrate; a second step of forming an insulator layer that becomes a capacitor insulator layer in said memory cell array region as well as in a peripheral circuit region which is formed on said semiconductor substrate, and forming a conductive layer that becomes a plate electrode on said insulator layer; a third step of forming a plate electrode formation resist pattern on said conductive layer, leaving said peripheral circuit region exposed; a fourth step of etching said conductive layer using said resist pattern as a mask so as to form a plate electrode made up of said conductive layer; a fifth step of forming an insulator layer used for a reduction in level difference in said peripheral circuit region using said resist pattern as a mask; a sixth step of, after removing said resist pattern, forming an interlayer insulator that flows upon heating in said memory cell array region as well as in said peripheral circuit region; and a seventh step of subjecting said interlayer insulator to a heat treatment in order that said interlayer insulator reflows.
Claim 12
Independent Claim
215 words
A method of fabricating a semiconductor memory device, said method comprising: a first step of forming a word line, a bit line, and a charge-storage electrode in a memory cell array region which is formed on a semiconductor substrate; a second step of forming an insulator layer that becomes a capacitor insulator layer in said memory cell array region as well as in a peripheral circuit region which is formed on said semiconductor substrate, and forming a conductive layer that becomes a plate electrode on said insulator layer; a third step of forming a plate electrode formation resist pattern on said conductive layer, leaving said peripheral circuit region exposed; a fourth step of etching said conductive layer using said resist pattern as a mask so as to form a plate electrode made up of said conductive layer; a fifth step of forming an insulator layer used for a reduction in level difference in said peripheral circuit region using said resist pattern as a mask; a sixth step of, after removing said resist pattern, forming an interlayer insulator that flows upon heating in said memory cell array region as well as in said peripheral circuit region; and a seventh step of subjecting said interlayer insulator to a heat treatment in order that said interlayer insulator reflows.
Claim 13
Dependent Claim
30 words
A semiconductor memory fabrication method as in claim 9, wherein said level difference reduction insulator layer is a silicon dioxide layer formed by means of a liquid phase epitaxy method.
Claim 14
Dependent Claim
58 words
A semiconductor memory fabrication method as in claim 9, wherein said third step includes a step of forming said resist pattern in such a way that said interlayer insulator, which lies in said peripheral circuit region and which is formed at said fifth step, has at the edge thereof a recess that surrounds said memory cell array region.
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