Patent US5404489A successfully refreshed from Google Patents.
US5404489A
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System and method for minimizing cache interruptions by inhibiting snoop cycles if access is to an exclusive page
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-05-02
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Granted: 1995-04-04
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Expires: 2014-05-02
Abstract
Abstract A memory property tagging apparatus is interfaced with one or more caches which are associated with one or more microprocessors of a multiprocessor system having shared memory and a bus network. The apparatus masks off any snoop cycles on the bus network if data corresponding to an address is exclusive to its associated microprocessor(s). The apparatus can specify to its associated one or more caches whether data is cacheable or not. The apparatus can specify to its associated one or more caches whether data is to be treated as write-through or write-back. Finally, the apparatus can translate preselected memory addresses on the bus network into input/output (IO) addresses.
Inventors
- 👤 Greg Woods
- 👤 Carol Bassett
- 👤 Robert Campbell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:49
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0888; G06F2212/00; G06F2212/20; G06F2212/206
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
195 words
A system for minimizing cache interruptions in a multiprocessor system having a shared memory, a processor, and a cache coupled to the processor, the cache having a shared memory space for storing data which is also stored in the shared memory and an exclusive memory space for storing data which is only stored in the cache, the system comprising: first means, coupled to the cache, for reading a data address from a bus network corresponding to data stored in a designated memory space of said cache; second means, coupled to said first means, for specifying a coherency property of said designated memory space, said coherency property indicating whether said designated memory space is included in the shared memory space or in the exclusive memory space of the cache, said second means generating a coherency signal representing said coherency property; and third means, coupled to said second means, for provoking a snoop strobe received from said bus network when said coherency property indicates said designated memory space is included in the shared memory space and for inhibiting said snoop strobe when said coherency property indicates said designated memory space is included in the exclusive memory space.
Claim 2
Independent Claim
195 words
A system for minimizing cache interruptions in a multiprocessor system having a shared memory, a processor, and a cache coupled to the processor, the cache having a shared memory space for storing data which is also stored in the shared memory and an exclusive memory space for storing data which is only stored in the cache, the system comprising: first means, coupled to the cache, for reading a data address from a bus network corresponding to data stored in a designated memory space of said cache; second means, coupled to said first means, for specifying a coherency property of said designated memory space, said coherency property indicating whether said designated memory space is included in the shared memory space or in the exclusive memory space of the cache, said second means generating a coherency signal representing said coherency property; and third means, coupled to said second means, for provoking a snoop strobe received from said bus network when said coherency property indicates said designated memory space is included in the shared memory space and for inhibiting said snoop strobe when said coherency property indicates said designated memory space is included in the exclusive memory space.
Claim 3
Dependent Claim
35 words
The system of claim 1, wherein said first means and said second means comprise a (SRAM) coupled to said bus network, said SRAM configured to receive said data address and to output said coherency signal.
Claim 4
Dependent Claim
17 words
The system of claim 2, wherein said SRAM comprises memory pages each with a 4 Kilobyte capacity.
Claim 5
Dependent Claim
17 words
The system of claim 2, wherein said SRAM comprises memory pages each with a 64 Kilobyte capacity.
Claim 6
Dependent Claim
51 words
The system of claim 2, wherein said third means comprises a discrete logic unit coupled to said SRAM and to said bus network, said discrete logic unit configured to receive said coherency signal from said SRAM and said snoop strobe from said bus network and to output a provoked snoop strobe.
Claim 7
Dependent Claim
87 words
The system of claim 1, further comprising: fourth means, coupled to said first means, for specifying a memory/input-output property of said designated memory space, said memory/input-output property indicating whether said designated memory space is allocated to the shared memory or to an input/output port, said fourth memory generating a memory/input-output signal representing said memory/input-output property; and fifth means, coupled to said fourth means, for translating said data address into an input-output address when said memory/input-output property indicates said designated memory space is allocated to said input-output port.
Claim 8
Dependent Claim
80 words
The system of claim 6, further comprising: sixth means, coupled to said first means, for specifying a write-through/write-back property indicating whether said designated memory space containing said data corresponding to said data address is to be configured as a write-back type cache or a write-through type cache, said sixth means configured to generate a WT/WB signal representing said write-through/write-back property; and seventh means, coupled to said sixth means and to the cache, for transferring said WT/WB signal to the cache.
Claim 9
Dependent Claim
100 words
The system of claim 7, further comprising: eighth means, coupled to said first means, for specifying a cacheability property indicating whether said designated memory space containing said data corresponding to said data address is a cacheable memory space or a non-cacheable memory space, and for generating a cacheability signal representing said cacheability property; and ninth means, coupled to said eighth means and to the cache, for enabling the cache when said cacheability signal indicates said designated memory space is cacheable memory space, and for disabling the cache when said cacheability signal indicates said designated memory space is non-cacheable memory space.
Claim 10
Dependent Claim
46 words
The system of claim 6, wherein said first means, said second means, and said fourth means comprise a static random access memory (SRAM) coupled to said bus network, said SRAM configured to receive said data address and to output said coherency signal and said memory/input-output signal.
Claim 11
Dependent Claim
56 words
The system of claim 9, wherein said third means comprises a discrete logic unit coupled to said SRAM and to said bus network, said discrete logic unit configured to receive said coherency property signal from said SRAM and said snoop strobe from said bus network and to output a provoked snoop strobe to said bus network.
Claim 12
Dependent Claim
33 words
The system of claim 10, wherein said fifth means comprises a second discrete logic unit coupled to said SRAM, said second discrete logic unit configured to receive said memory/input-output signal from said SRAM.
Claim 13
Independent Claim
164 words
A method for minimizing cache interruptions in a computer system having one or more caches, a plurality of processors, a shared memory, and a bus network coupling the one or more caches with the shared memory, each of the one or more caches comprising memory pages, the method comprising the steps of: (1) specifying each memory page of each of the one or more caches as either an exclusive memory page or as a shared memory page, said shared memory page configured to store data which is shared with respect to the plurality of processors; (2) sensing on the bus network that an access to said shared memory has been initiated; (3) specifying whether said access is to said exclusive memory page in said shared memory based on an address associated with said access to said shared memory; and (4) generating a signal indicating that a snoop cycle on the bus network can be ignored if said access is to said exclusive memory page.
Claim 14
Independent Claim
164 words
A method for minimizing cache interruptions in a computer system having one or more caches, a plurality of processors, a shared memory, and a bus network coupling the one or more caches with the shared memory, each of the one or more caches comprising memory pages, the method comprising the steps of: (1) specifying each memory page of each of the one or more caches as either an exclusive memory page or as a shared memory page, said shared memory page configured to store data which is shared with respect to the plurality of processors; (2) sensing on the bus network that an access to said shared memory has been initiated; (3) specifying whether said access is to said exclusive memory page in said shared memory based on an address associated with said access to said shared memory; and (4) generating a signal indicating that a snoop cycle on the bus network can be ignored if said access is to said exclusive memory page.
Claim 15
Dependent Claim
84 words
The method of claim 12, wherein the computer system further comprises one or more input/output ports, the method further comprising the steps of: (5) retrieving a shared memory address from the bus network; (6) determining whether said shared memory address corresponds to a memory space identifying the shared memory or the one or more input/output ports; and (7) translating said shared memory address into an input/output address on the bus network if said shared memory address corresponds to the one or more input/output ports.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |