Dynamic random access memory device with precharging unit preventing counter electrodes of storage capacitors from voltage fluctuation

Claim 1

A dynamic random access memory device comprising: a) a plurality of memory cells respectively storing data bits in the form of electric charges, each of said memory cells comprising a first switching transistor and a storage capacitor coupled in series, said storage capacitor having an accumulating electrode coupled with a source node of said first switching transistor and a counter electrode opposed to said accumulating electrode; b) an addressing system responsive to external address bits for allowing said plurality of memory cells to selectively become accessible; c) a plurality of digit lines selectively coupled with a drain node of said first switching transistor of each of said memory cells, and forming digit line pairs for propagating data bits in the form of a potential difference; d) an intermediate voltage generator for generating an intermediate voltage having a level between a high voltage level and a low voltage level, and for supplying said intermediate voltage via a common voltage line to said counter electrode of each storage capacitor; e) a precharging unit, coupled to said plurality of digit lines, said precharging unit simultaneously coupling said plurality of digit lines to a common node in a precharging stage, before said addressing system allows said plurality of memory cells to selectively become accessible, to balancing said plurality of digit lines with one another; and f) a cut-off means, coupled between said common voltage line and said common node, for electrically isolating said common voltage line from said precharging unit during said precharging stage to prevent voltage fluctuation at said counter electrode of each said storage capacitor during said precharging stage.