EP0151898A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and appartus for equilibrating a memory cell
Assignee: STMicroelectronics lnc USA
•
Filing: 1984-12-28
•
Granted: —
•
Expires: 2004-12-28
Abstract
Abstract 57 An equilibration circuit for dynamic RAMs connects the true and complement bit lines to the cell plate and to a reference voltage.
Inventors
- 👤 Ronald Thomas Taylor
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 13:13
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C11/403; G11C11/404; G11C11/4074
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
155 words
A semiconductor memory circuit having an array of memory cells, each cell having a cell plate with one terminal of a capacitor connected to it and a set of true and complement bit lines connected to selected ones of said cells; and an equilibration circuit for connecting, in pairs, selected true and complement bit lines to an equilibration voltage means; characterized in that: said equilibration circuit comprises first and second transistors, controlled by said equilibration voltage means, each having a first terminal connected to an equilibration node and a second terminal connected to one of said true and complement bit lines; and said equilibration node is connected directly to a cell plate node common to a cell plate of at least two of said array of cells and said equilibration node is connected to voltage means for maintaining said equilibration node at a predetermined voltage substantially half way between a circuit supply voltage and ground.
Claim 2
Dependent Claim
155 words
A semiconductor memory circuit having an array of memory cells, each cell having a cell plate with one terminal of a capacitor connected to it and a set of true and complement bit lines connected to selected ones of said cells; and an equilibration circuit for connecting, in pairs, selected true and complement bit lines to an equilibration voltage means; characterized in that: said equilibration circuit comprises first and second transistors, controlled by said equilibration voltage means, each having a first terminal connected to an equilibration node and a second terminal connected to one of said true and complement bit lines; and said equilibration node is connected directly to a cell plate node common to a cell plate of at least two of said array of cells and said equilibration node is connected to voltage means for maintaining said equilibration node at a predetermined voltage substantially half way between a circuit supply voltage and ground.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.