Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit

Claim 2

An ESD/EOS protection circuit for protecting an integrated circuit comprising: a. a MOS transistor having a drain region, a source region and a gate; b. at least one source contact located above said source region at a first distance from said gate, wherein said at least one source contact comprises a plurality of source contacts arranged into a plurality of rows and columns; c. at least one drain contact located above said drain region at a second distance from said gate, wherein said first distance is smaller than said second distance.

Claim 3

The ESD/EOS protection circuit of claim 1, wherein said source region and said drain region comprise approximately the same amount of area.

Claim 4

The ESD/EOS protection circuit of claim 1, wherein said first distance is less than 2 microns.

Claim 5

The ESD/EOS protection circuit of claim 1, wherein said first distance is a lithographic minimum distance.

Claim 6

The ESD/EOS protection circuit of claim 1, wherein said at least one drain contact comprises a plurality of drain contacts arranged in a row.

Claim 7

The ESD/EOS protection circuit of claim 1, further comprising: a. a first metal layer extending over said drain region and in contact with said drain region via said at least one drain contact; b. a second metal layer extending over said source region and in contact with said source region via said at least one source contact; c. a third metal layer extending over said MOS transistor; and d. a plurality of metal-to-metal contacts for connecting said third metal layer with said second metal layer.

Claim 8

An ESD/EOS protection circuit for protecting an integrated circuit comprising: a. a MOS transistor arranged in a multi-finger configuration having a plurality of drain regions, a plurality of source regions and a plurality of gates, wherein each of said gates is located between one of said source regions and one of said drain regions; b. a plurality of source contacts located above each of said source regions at a first distance from at least one of said plurality of gates; c. a plurality of drain contacts located above each of said drain regions at a second distance from at least one of said plurality of gates, wherein said first distance is smaller than said second distance; d. a first metal layer extending over and substantially covering each of said drain regions and in contact with each of said drain regions via said plurality of drain contacts; e. a second metal layer extending over and substantially covering each of said source regions and in contact with each of said source regions via said plurality of source contacts; f. a third metal layer extending over and substantially covering said MOS transistor; and g. a plurality of metal-to-metal contacts for connecting said third metal layer with said second metal layer over each of said source regions.

Claim 9

An ESD/EOS protection circuit for protecting an integrated circuit comprising: a. a MOS transistor arranged in a multi-finger configuration having a plurality of drain regions, a plurality of source regions and a plurality of gates, wherein each of said gates is located between one of said source regions and one of said drain regions; b. a plurality of source contacts located above each of said source regions at a first distance from at least one of said plurality of gates; c. a plurality of drain contacts located above each of said drain regions at a second distance from at least one of said plurality of gates, wherein said first distance is smaller than said second distance; d. a first metal layer extending over and substantially covering each of said drain regions and in contact with each of said drain regions via said plurality of drain contacts; e. a second metal layer extending over and substantially covering each of said source regions and in contact with each of said source regions via said plurality of source contacts; f. a third metal layer extending over and substantially covering said MOS transistor; and g. a plurality of metal-to-metal contacts for connecting said third metal layer with said second metal layer over each of said source regions.

Claim 10

The ESD/EOS protection circuit of claim 7, wherein said plurality of source regions and said plurality of drain regions comprise approximately the same amount of area.

Claim 11

The ESD/EOS protection circuit of claim 7, wherein said first distance is less than 2 microns.

Claim 12

The ESD/EOS protection circuit of claim 7, wherein said first distance is a design minimum.

Claim 13

The ESD/EOS protection circuit of claim 7, wherein said plurality of drain contacts are arranged in a row above each of said drain regions.

Claim 14

The ESD/EOS protection circuit of claim 7, wherein said third metal layer is connected to a ground and said first metal layer is connected to a protected pad.

Claim 15

The ESD/EOS protection circuit of claim 7, wherein said plurality of source contacts and said plurality of metal-to-metal contacts are arranged in a plurality of alternating rows over each of said source regions.