Method of forming multilayered wiring

Claim 1

A method of forming a multilayered wiring, comprising the steps of: (a) forming a first wiring layer on the insulative surface of a substrate; (b) forming an interlayer insulating film on said first wiring layer and covering the insulating surface of said substrate; (c) forming a reflection preventing film on said interlayer insulating film; (d) forming a resist layer on said reflection preventing film, and exposing and developing said resist layer to form an opening corresponding to a contact hole; (e) selectively etching the laminated structure of said reflection preventing film and said interlayer insulating film by using said resist film as a mask to form said contact hole down to the surface of said first wiring layer; (f) removing at least said resist layer among said resist layer and said reflection preventing layer; and (g) forming a second wiring layer on said interlayer insulating film and electrically connecting said second wiring layer to said first wiring layer via said contact hole.

Claim 2

A method of forming a multilayered wiring, comprising the steps of: (a) forming a first wiring layer on the insulative surface of a substrate; (b) forming an interlayer insulating film on said first wiring layer and covering the insulating surface of said substrate; (c) forming a reflection preventing film on said interlayer insulating film; (d) forming a resist layer on said reflection preventing film, and exposing and developing said resist layer to form an opening corresponding to a contact hole; (e) selectively etching the laminated structure of said reflection preventing film and said interlayer insulating film by using said resist film as a mask to form said contact hole down to the surface of said first wiring layer; (f) removing at least said resist layer among said resist layer and said reflection preventing layer; and (g) forming a second wiring layer on said interlayer insulating film and electrically connecting said second wiring layer to said first wiring layer via said contact hole.

Claim 7

A method of manufacturing a multi-level wiring structure for a semiconductor device provided on a semiconductor substrate, comprising the steps of: (a) providing the semiconductor substrate; (b) forming a thick field insulating film in the semiconductor substrate; (c) forming a first level metal wiring on and a source and a drain region in the semiconductor substrate; (d) forming a first level interlayer insulating film over the first level metal wiring and the semiconductor substrate, the first level interlayer insulating film having a corrugated structure caused by the thick field insulating film, and the first level wiring; (e) forming a second level metal wiring on the first level interlayer insulating film, the second level metal wiring having an uneven surface caused by the first level interlayer insulating film and a high reflectance property with respect to ultra-violet light; (f) forming a second level interlayer insulating film over the second level metal wiring and the first level interlayer insulating film; (g) depositing a reflection preventing film having a thickness of at least about 80 nm over the second level interlayer insulating film; (h) forming a positive type resist layer over the reflection preventing film; (i) subjecting the semiconductor substrate to ultra-violet light to pattern a contact hole reaching the second level metal wiring film, wherein the reflection preventing film constrains a multi-reflection of the ultra-violet light to thereby improve patterning accuracy.

Claim 8

A method of manufacturing a multi-level wiring structure for a semiconductor device provided on a semiconductor substrate, comprising the steps of: (a) providing the semiconductor substrate; (b) forming a thick field insulating film in the semiconductor substrate; (c) forming a first level metal wiring on and a source and a drain region in the semiconductor substrate; (d) forming a first level interlayer insulating film over the first level metal wiring and the semiconductor substrate, the first level interlayer insulating film having a corrugated structure caused by the thick field insulating film, and the first level wiring; (e) forming a second level metal wiring on the first level interlayer insulating film, the second level metal wiring having an uneven surface caused by the first level interlayer insulating film and a high reflectance property with respect to ultra-violet light; (f) forming a second level interlayer insulating film over the second level metal wiring and the first level interlayer insulating film; (g) depositing a reflection preventing film having a thickness of at least about 80 nm over the second level interlayer insulating film; (h) forming a positive type resist layer over the reflection preventing film; (i) subjecting the semiconductor substrate to ultra-violet light to pattern a contact hole reaching the second level metal wiring film, wherein the reflection preventing film constrains a multi-reflection of the ultra-violet light to thereby improve patterning accuracy.

Claim 9

A method of manufacturing a multi-level wiring structure for a semiconductor device having a plurality of device elements on a semiconductor substrate, comprising the steps of: (a) providing the semiconductor substrate; (b) forming the plurality of device elements on the semiconductor substrate; (c) forming a first interlayer insulating film over the device elements, the first level interlayer insulating film having a corrugated surface caused by the device elements; (d) forming a metal wiring layer, having an uneven surface, over the first level interlayer insulating film; (e) forming a second interlayer insulating film over the metal wiring layer; (f) depositing a reflection preventing film having a thickness of at least about 80 nm over the second interlayer insulating film; (g) forming a resist layer over the reflection preventing film; (h) subjecting the semiconductor substrate to ultra-violet light to pattern a contact hole reaching the metal wiring layer, wherein the reflection preventing film constrains a multi-reflection of the ultra-violet to thereby improve patterning accuracy.

Claim 10

A method of manufacturing a multi-level wiring structure for a semiconductor device having a plurality of device elements on a semiconductor substrate, comprising the steps of: (a) providing the semiconductor substrate; (b) forming the plurality of device elements on the semiconductor substrate; (c) forming a first interlayer insulating film over the device elements, the first level interlayer insulating film having a corrugated surface caused by the device elements; (d) forming a metal wiring layer, having an uneven surface, over the first level interlayer insulating film; (e) forming a second interlayer insulating film over the metal wiring layer; (f) depositing a reflection preventing film having a thickness of at least about 80 nm over the second interlayer insulating film; (g) forming a resist layer over the reflection preventing film; (h) subjecting the semiconductor substrate to ultra-violet light to pattern a contact hole reaching the metal wiring layer, wherein the reflection preventing film constrains a multi-reflection of the ultra-violet to thereby improve patterning accuracy.

Claim 13

A method of forming multilayered wiring, comprising the steps of: (a) forming a conductive layer on a semiconductor body; (b) forming an interlayer insulating film on said conductive layer; (c) forming a reflection prevention film on said interlayer insulating film, said reflection prevention film suppressing light reflection; (d) forming a resist pattern on said reflection prevention film; and (e) forming a contact hole down to the surface of said conductive layer through said reflection prevention film and said interlayer insulating film by using said resist pattern.

Claim 14

A method of forming multilayered wiring, comprising the steps of: (a) forming a conductive layer on a semiconductor body; (b) forming an interlayer insulating film on said conductive layer; (c) forming a reflection prevention film on said interlayer insulating film, said reflection prevention film suppressing light reflection; (d) forming a resist pattern on said reflection prevention film; and (e) forming a contact hole down to the surface of said conductive layer through said reflection prevention film and said interlayer insulating film by using said resist pattern.

Claim 18

A method of forming a multilayered wiring, comprising the steps of: (a) forming a first wiring layer on a semiconductor body; (b) forming an interlayer insulating film on said first wiring layer; (c) forming a reflection prevention film having a thickness of about 80 nm or more on said interlayer insulating film, said reflection prevention film suppressing light reflection; (d) forming a resist pattern on said reflection prevention film; and (e) forming a contact hole down to the surface of said first wiring layer through said reflection prevention film and said interlayer insulating film by using said resist pattern.

Claim 19

A method of forming a multilayered wiring, comprising the steps of: (a) forming a first wiring layer on a semiconductor body; (b) forming an interlayer insulating film on said first wiring layer; (c) forming a reflection prevention film having a thickness of about 80 nm or more on said interlayer insulating film, said reflection prevention film suppressing light reflection; (d) forming a resist pattern on said reflection prevention film; and (e) forming a contact hole down to the surface of said first wiring layer through said reflection prevention film and said interlayer insulating film by using said resist pattern.