Nonvolatile semiconductor memory device having a status register and test method for the same

Claim 2

A nonvolatile semiconductor memory comprising: a plurality of word lines and a plurality of bit lines arranged in a grid pattern; a memory cell matrix consisting of electrically erasable nonvolatile memory cells whose gates are connected to said word lines and whose drains are connected to said bit lines, each of said memory cells being formed at one of the intersections between said word lines and said bit lines; a sense amplifier for outputting a signal corresponding to a logic value "1" or "0" by detecting the amount of current that varies according to whether the memory cell located at the intersection between a selected word line and a selected bit line is conducting or nonconducting; a write/erase timing circuit for automatically performing timing control necessary for writing data into and erasing data from said memory cells; a status register for storing the operating state of said memory at the completion of the operation of said write/erase timing circuit in such a manner that the stored state is accessible externally; dummy cells provided outside the address of said memory cell matrix and consisting of electrically unalterable cells each preset to one of two states so that said sense amplifier outputs a logic value "1" or "0" depending on the state of the accessed dummy cell; and control means for performing control so that said dummy cells are accessed when said write/erase timing circuit is operated to test the performance of said status register.

Claim 3

A performance test method for a nonvolatile semiconductor memory which comprises: a plurality of word lines and a plurality of bit lines arranged in a grid pattern; a memory cell matrix consisting of electrically erasable nonvolatile memory cells whose gates are connected to said word lines and whose drains are connected to said bit lines, each of said memory cells being formed at one of the intersections between said word lines and said bit lines; a sense amplifier for outputting a signal corresponding to a logic value "1" or "0" by detecting the amount of current that varies according to whether the memory cell located at the intersection between a selected word line and a selected bit line is conducting or nonconducting; a write/erase timing circuit for automatically performing timing control necessary for writing data into and erasing data from said memory cells; a status register for storing the operating state of said memory at the completion of the operation of said write/erase timing circuit in such a manner that the stored state is accessible externally, and dummy cells provided outside the address of said memory cell matrix and consisting of electrically unalterable cells each preset to one of two states so that said sense amplifier outputs a logic value "1" or "0" depending on the state of the accessed dummy cell, said method comprising the steps of: providing a write failure state or an erasure failure state by attempting to write a logic value "0" to a cell, of said dummy cells, preset to a logic value "1", or by attempting to erase a cell preset to a logic value "0" and confirming that the cell does not change to the logic value "1"; providing a write normal state by attempting to write a logic value "1" to a cell, of said dummy cells, preset to a logic value "1", or by attempting to write a logic value "0" to a cell preset to a logic value "0"; providing an erasure failure state by attempting to erase a cell, of said dummy cells, preset to a value corresponding to a written state; or an erasure normal state by attempting to erase a cell, of said dummy cells, preset to a value corresponding to an unwritten state.

Claim 4

A performance test method for a nonvolatile semiconductor memory which comprises: a plurality of word lines and a plurality of bit lines arranged in a grid pattern; a memory cell matrix consisting of electrically erasable nonvolatile memory cells whose gates are connected to said word lines and whose drains are connected to said bit lines, each of said memory cells being formed at one of the intersections between said word lines and said bit lines; a sense amplifier for outputting a signal corresponding to a logic value "1" or "0" by detecting the amount of current that varies according to whether the memory cell located at the intersection between a selected word line and a selected bit line is conducting or nonconducting; a write/erase timing circuit for automatically performing timing control necessary for writing data into and erasing data from said memory cells; a status register for storing the operating state of said memory at the completion of the operation of said write/erase timing circuit in such a manner that the stored state is accessible externally, and dummy cells provided outside the address of said memory cell matrix and consisting of electrically unalterable cells each preset to one of two states so that said sense amplifier outputs a logic value "1" or "0" depending on the state of the accessed dummy cell, said method comprising the steps of: providing a write failure state or an erasure failure state by attempting to write a logic value "0" to a cell, of said dummy cells, preset to a logic value "1", or by attempting to erase a cell preset to a logic value "0" and confirming that the cell does not change to the logic value "1"; providing a write normal state by attempting to write a logic value "1" to a cell, of said dummy cells, preset to a logic value "1", or by attempting to write a logic value "0" to a cell preset to a logic value "0"; providing an erasure failure state by attempting to erase a cell, of said dummy cells, preset to a value corresponding to a written state; or an erasure normal state by attempting to erase a cell, of said dummy cells, preset to a value corresponding to an unwritten state.