Method of manufacturing a hetero bipolar transistor

Claim 1

A method of manufacturing a hetero bipolar transistor, comprising the steps of: preparing a semiconductor substrate; forming a first polycrystalline silicon layer on an entire surface of said semiconductor substrate; selectively removing said first polycrystalline silicon layer to expose a surface of said semiconductor substrate; forming an oxynitride layer on an entire surface of the resultant structure in a manner to cover a side wall of said first polycrystalline silicon layer; forming a first insulating layer on the resultant structure; selectively removing said first insulating layer and said oxynitride layer to form an opening extending to reach said semiconductor substrate, said side wall of said first polycrystalline silicon layer not being exposed by said opening; forming a laminate structure consisting of a first semiconductor layer, a second semiconductor layer and a third semiconductor layer by means of an epitaxial vapor growth technique, said opening being filled with said laminate structure, and at least a side wall of said second semiconductor layer being in contact with the side wall of said oxynitride layer; selectively removing said insulating layer and said oxynitride layer to allow the remaining portions of these insulating layer and oxynitride layer to surround said laminate structure consisting of the first, second and third semiconductor layers; removing the remaining portion of said oxynitride layer to form a cavity; and forming a fourth semiconductor layer by means of an epitaxial vapor growth technique to cover the first polycrystalline silicon layer and the side walls of the laminate structure consisting of the first, second and third semiconductor layers said cavity being filled with said fourth semiconductor layer.

Claim 2

A method of manufacturing a hetero bipolar transistor, comprising the steps of: preparing a semiconductor substrate; forming a first polycrystalline silicon layer on an entire surface of said semiconductor substrate; selectively removing said first polycrystalline silicon layer to expose a surface of said semiconductor substrate; forming an oxynitride layer on an entire surface of the resultant structure in a manner to cover a side wall of said first polycrystalline silicon layer; forming a first insulating layer on the resultant structure; selectively removing said first insulating layer and said oxynitride layer to form an opening extending to reach said semiconductor substrate, said side wall of said first polycrystalline silicon layer not being exposed by said opening; forming a laminate structure consisting of a first semiconductor layer, a second semiconductor layer and a third semiconductor layer by means of an epitaxial vapor growth technique, said opening being filled with said laminate structure, and at least a side wall of said second semiconductor layer being in contact with the side wall of said oxynitride layer; selectively removing said insulating layer and said oxynitride layer to allow the remaining portions of these insulating layer and oxynitride layer to surround said laminate structure consisting of the first, second and third semiconductor layers; removing the remaining portion of said oxynitride layer to form a cavity; and forming a fourth semiconductor layer by means of an epitaxial vapor growth technique to cover the first polycrystalline silicon layer and the side walls of the laminate structure consisting of the first, second and third semiconductor layers said cavity being filled with said fourth semiconductor layer.