US5398324A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sytem for efficiently storing same data in duplex storage by using single storage controller
Assignee: NEC Corp
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Filing: 1992-06-15
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Granted: 1995-03-14
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Expires: 2012-06-15
Abstract
Abstract In a system for storing same data in first and second storages, a central controller for producing a duplex write control signal on a bus. An I/O processor processes the duplex write control signal received from the bus into first and second write control signals to deliver the first and the second write control signals to first and second DMA controllers connected to the first and the second storages. A request controller selects, as a first selected request, that one of first and second data transfer requests simultaneously produced by the first and the second DMA controllers in response to the first and the second write control signals. Supposing that the first selected request is the first data transfer request, a data buffer controller controls the first DMA controller in response to the first selected request to read the data from a main memory on the bus and to write the data in the first storage. Simultaneously, the data buffer controller makes a data buffer memory memorize the data. When the request controller subsequently selects the second data transfer request as a second selected request, the data buffer controller reads the data from the data buffer memory, and makes the second DMA controller write the data in the second storage.
Inventors
- 👤 Naoki Matida
- 👤 Atsuki Muramatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 01:43
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2053; G06F11/2056; G06F11/2087; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F3/00; G06F3/06; G06F3/0601; G06F3/0628; G06F3/0655; G06F3/0656
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
652 words
An information processing system for use in combination with a duplex storage having first and a second storages, the information processing system comprising: a bus; a main memory, including a data area, connected to said bus; a central processor including a control signal producer connected to said bus for producing a duplex write control signal indicative of data transfer from said data area to said first and said second storages and for delivering said duplex write control signal to said bus; and a duplex storage controller including: an input-output controller connected to said bus for producing a first and a second write control signal in response to said duplex write control signal received from said bus, said first write control signal being indicative of data transfer from said data area to said first storage, and said second write control signal being indicative of data transfer from said data area to said second storage; a first DMA controller including a first local memory connected to said input-output controller for memorizing said first write control signal as a first memorized write control signal and a first DMA control unit connected to said first storage, said bus and said first local memory for producing a first data transfer request in response to said first memorized write control signal; a second DMA controller including a second local memory connected to said input-output controller for memorizing said second write control signal as a second memorized write control signal and a second DMA control unit connected to said second storage, said bus and said second local memory for producing a second data transfer request in response to said second memorized write control signal; a request controller connected to said first and said second DMA control units for selecting a particular one of said first and said second data transfer requests as a first selected transfer request to produce said first selected transfer request and a particular unit signal representative of a particular one of a said first and said second DMA control units that produces said first selected transfer request; a data buffer memory connected to said bus; and a data buffer controller connected to said first and said second DMA control units for controlling said particular one of said first and said second DMA control units in response to said first selected transfer request and said particular unit signal to read data from said data area on said bus and to write said data in a particular one of said first and said second storages connected to said particular one of said first and said second DMA control units, said data buffer controller connected to said data buffer memory for making said data buffer memory memorize said data produced on said bus; said particular one of said first and said second DMA control units producing an end signal representative of an end of the data transfer from said data area to said particular one of said first and said second storages; said request controller selecting, in response to said end signal, a different one of said first and said second data transfer requests as a second selected transfer request to produce said second selected transfer request and a different unit signal representative of a different one of said first and said second DMA control units that produces said second selected transfer request; said data buffer memory connected to said first and said second DMA control units; said data buffer controller reading said data from said data buffer memory in response to said second selected transfer request and said different unit signal and controlling said different one of said first and said second DMA control units in response to said second selected transfer request and said different unit signal to write said data in a different one of said first and said second storages connected to said different one of said first and said second DMA control units.
Claim 2
Dependent Claim
652 words
An information processing system for use in combination with a duplex storage having first and a second storages, the information processing system comprising: a bus; a main memory, including a data area, connected to said bus; a central processor including a control signal producer connected to said bus for producing a duplex write control signal indicative of data transfer from said data area to said first and said second storages and for delivering said duplex write control signal to said bus; and a duplex storage controller including: an input-output controller connected to said bus for producing a first and a second write control signal in response to said duplex write control signal received from said bus, said first write control signal being indicative of data transfer from said data area to said first storage, and said second write control signal being indicative of data transfer from said data area to said second storage; a first DMA controller including a first local memory connected to said input-output controller for memorizing said first write control signal as a first memorized write control signal and a first DMA control unit connected to said first storage, said bus and said first local memory for producing a first data transfer request in response to said first memorized write control signal; a second DMA controller including a second local memory connected to said input-output controller for memorizing said second write control signal as a second memorized write control signal and a second DMA control unit connected to said second storage, said bus and said second local memory for producing a second data transfer request in response to said second memorized write control signal; a request controller connected to said first and said second DMA control units for selecting a particular one of said first and said second data transfer requests as a first selected transfer request to produce said first selected transfer request and a particular unit signal representative of a particular one of a said first and said second DMA control units that produces said first selected transfer request; a data buffer memory connected to said bus; and a data buffer controller connected to said first and said second DMA control units for controlling said particular one of said first and said second DMA control units in response to said first selected transfer request and said particular unit signal to read data from said data area on said bus and to write said data in a particular one of said first and said second storages connected to said particular one of said first and said second DMA control units, said data buffer controller connected to said data buffer memory for making said data buffer memory memorize said data produced on said bus; said particular one of said first and said second DMA control units producing an end signal representative of an end of the data transfer from said data area to said particular one of said first and said second storages; said request controller selecting, in response to said end signal, a different one of said first and said second data transfer requests as a second selected transfer request to produce said second selected transfer request and a different unit signal representative of a different one of said first and said second DMA control units that produces said second selected transfer request; said data buffer memory connected to said first and said second DMA control units; said data buffer controller reading said data from said data buffer memory in response to said second selected transfer request and said different unit signal and controlling said different one of said first and said second DMA control units in response to said second selected transfer request and said different unit signal to write said data in a different one of said first and said second storages connected to said different one of said first and said second DMA control units.
Claim 3
Dependent Claim
146 words
An information processing system as claimed in claim 1, wherein: said duplex storage controller further comprises a bus controller connected to said bus; said data buffer controller being connected to said bus controller for making said bus controller acquire said bus in response to said first selected request; said data buffer controller controlling, after said bus controller acquires said bus, said particular one of said first and said second DMA control units in response to said first selected transfer request and said particular unit signal to read data from said data area on said bus and to write said data in a particular one of said first and said second storages that is connected to said particular one of said first and said second DMA control units; and said dada buffer controller making said bus controller release said bus in response to said second selected request.
Claim 4
Dependent Claim
651 words
A duplex storage controller for an information processing system, the processing system comprising: a duplex storage including a first and a second storage: a bus; a main memory including a data area connected to said bus; and a central processor including a control signal producer connected to said bus for producing a duplex write control signal indicative of data transfer from said data area to said first and said second storages and for delivering said duplex write control signal to said bus; said duplex storage controller comprising: an input-output controller connected to said bus for producing a first and a second write control signal in response to said duplex write control signal received from said bus, said first write control signal being indicative of data transfer from said data area to said first storage, and said second write control signal being indicative of data transfer from said data area to said second storage; a first DMA controller including a first local memory connected to said input-output controller for memorizing said first write control signal as a first memorized write control signal and a first DMA control unit connected to said first storage, said bus, and said first local memory for producing a first data transfer request in response to said first write control signal; a second DMA controller comprising a second local memory connected to said input-output controller for memorizing said second write control signal as a second memorized write control signal and a second DMA control unit connected to said second storage, said bus, and said second local memory for producing a second data transfer request in response to said second memorized write control signal; a request controller connected to said first and said second DMA control units for selecting a particular one of said first and said second data transfer requests as a first selected transfer request to produce said first selected transfer request and a particular unit signal representative of a particular one of said first and said second DMA control units that produces said first selected transfer request; a data buffer memory connected to said bus; and a data buffer controller connected to said first and said second DMA control units for controlling said particular one of said first and said second DMA control units in response to said first selected transfer request and said particular unit signal to read data from said data area on said bus and to write said data in a particular one of said first and said second storages that is connected to said particular one of said first and said second DMA control units, said data buffer controller being furthermore connected to said data buffer memory for making said data buffer memory memorize said data produced on said bus, said particular one of said first and said second DMA control units producing an end signal representative of an end of the data transfer from said data area to said particular one of said first and said second storages; said request controller selecting, in response to said end signal, a different one of said first and said second data transfer requests as a second selected transfer request and a different unit signal representative of a different one of said first and said second DMA control units that produces said second selected transfer request; said data buffer memory connected to said first and said second DMA control units; and said data buffer controller reading said data from said data buffer memory in response to said second selected transfer request and said different unit signal and for controlling said different one of said first and said second DMA control units in response to said second selected transfer request and said different unit signal to write said data in a different one of said first and said second storages that is connected to said different one of said first and said second DMA control units.
Claim 5
Dependent Claim
651 words
A duplex storage controller for an information processing system, the processing system comprising: a duplex storage including a first and a second storage: a bus; a main memory including a data area connected to said bus; and a central processor including a control signal producer connected to said bus for producing a duplex write control signal indicative of data transfer from said data area to said first and said second storages and for delivering said duplex write control signal to said bus; said duplex storage controller comprising: an input-output controller connected to said bus for producing a first and a second write control signal in response to said duplex write control signal received from said bus, said first write control signal being indicative of data transfer from said data area to said first storage, and said second write control signal being indicative of data transfer from said data area to said second storage; a first DMA controller including a first local memory connected to said input-output controller for memorizing said first write control signal as a first memorized write control signal and a first DMA control unit connected to said first storage, said bus, and said first local memory for producing a first data transfer request in response to said first write control signal; a second DMA controller comprising a second local memory connected to said input-output controller for memorizing said second write control signal as a second memorized write control signal and a second DMA control unit connected to said second storage, said bus, and said second local memory for producing a second data transfer request in response to said second memorized write control signal; a request controller connected to said first and said second DMA control units for selecting a particular one of said first and said second data transfer requests as a first selected transfer request to produce said first selected transfer request and a particular unit signal representative of a particular one of said first and said second DMA control units that produces said first selected transfer request; a data buffer memory connected to said bus; and a data buffer controller connected to said first and said second DMA control units for controlling said particular one of said first and said second DMA control units in response to said first selected transfer request and said particular unit signal to read data from said data area on said bus and to write said data in a particular one of said first and said second storages that is connected to said particular one of said first and said second DMA control units, said data buffer controller being furthermore connected to said data buffer memory for making said data buffer memory memorize said data produced on said bus, said particular one of said first and said second DMA control units producing an end signal representative of an end of the data transfer from said data area to said particular one of said first and said second storages; said request controller selecting, in response to said end signal, a different one of said first and said second data transfer requests as a second selected transfer request and a different unit signal representative of a different one of said first and said second DMA control units that produces said second selected transfer request; said data buffer memory connected to said first and said second DMA control units; and said data buffer controller reading said data from said data buffer memory in response to said second selected transfer request and said different unit signal and for controlling said different one of said first and said second DMA control units in response to said second selected transfer request and said different unit signal to write said data in a different one of said first and said second storages that is connected to said different one of said first and said second DMA control units.
Claim 6
Dependent Claim
150 words
A duplex storage controller as claimed in claim 3, wherein: said duplex storage controller further comprises a bus controller connected to said bus; said data buffer controller being connected to said bus controller for making said bus controller acquire said bus in response to said first selected request; said data buffer controller being for controlling, after said bus controller acquires said bus, said particular one of said first and said second DMA control units in response to said first selected transfer request and said particular unit signal to read data from said data area on said bus and to write said data in a particular one of said first and said second storages that is connected to said particular one of said first and said second DMA control units; and said data buffer controller being for making said bus controller release said bus in response to said second selected request.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |