US5397946A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-voltage sensor for integrated circuits
Assignee: Texas Instruments Inc
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Filing: 1993-10-26
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Granted: 1995-03-14
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Expires: 2013-10-26
Abstract
Abstract The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.
Inventors
- 👤 Phat C. Truong
- 👤 Tim M. Coffman
- 👤 Sung-Wei Lin
- 👤 T. Damodar Reddy
- 👤 Dennis R. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:17
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/143; G11C16/00; G11C16/02; G11C16/06; G11C16/22; G11C16/225
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
249 words
A high-voltage sensor circuit for an integrated circuit, said integrated circuit including a connection pin, a supply-voltage pin and a reference-voltage pin, said sensor circuit comprising: a first transistor with a first source-drain a second source-drain and a gate, said first source-drain of said first transistor coupled to said connection pin; a second transistor with a first source-drain a second source-drain and a gate, said first source-drain of said second transistor coupled to said second source-drain of said first transistor, said gate of said second transistor coupled to said supply-voltage pin; a third transistor with a first source-drain a second source drain and a gate, said first source drain of said third transistor coupled to said connection pin, said gate of said third transistor coupled to said gate of said first transistor; a fourth transistor with a first source drain a second source-drain and a gate, said first source-drain of said fourth transistor coupled to said second source-drain of said third transistor, said gate of said fourth transistor coupled to said gate of said second transistor; a fifth transistor with a first source drain a second source-drain and a gate, said first source-drain of said fifth transistor coupled to said second source-drain of said fourth transistor; said second source-drain of said fifth transistor coupled to an output, said gate of said fifth transistor coupled to said second source-drain of said second transistor; and a voltage reference circuit coupled between said gate of said fifth transistor and said reference-voltage pin.
Claim 2
Dependent Claim
249 words
A high-voltage sensor circuit for an integrated circuit, said integrated circuit including a connection pin, a supply-voltage pin and a reference-voltage pin, said sensor circuit comprising: a first transistor with a first source-drain a second source-drain and a gate, said first source-drain of said first transistor coupled to said connection pin; a second transistor with a first source-drain a second source-drain and a gate, said first source-drain of said second transistor coupled to said second source-drain of said first transistor, said gate of said second transistor coupled to said supply-voltage pin; a third transistor with a first source-drain a second source drain and a gate, said first source drain of said third transistor coupled to said connection pin, said gate of said third transistor coupled to said gate of said first transistor; a fourth transistor with a first source drain a second source-drain and a gate, said first source-drain of said fourth transistor coupled to said second source-drain of said third transistor, said gate of said fourth transistor coupled to said gate of said second transistor; a fifth transistor with a first source drain a second source-drain and a gate, said first source-drain of said fifth transistor coupled to said second source-drain of said fourth transistor; said second source-drain of said fifth transistor coupled to an output, said gate of said fifth transistor coupled to said second source-drain of said second transistor; and a voltage reference circuit coupled between said gate of said fifth transistor and said reference-voltage pin.
Claim 3
Dependent Claim
20 words
The circuit of claim 1, wherein each of said first, second, third, fourth and fifth transistors is a P-channel transistor.
Claim 4
Dependent Claim
28 words
The circuit of claim 1, wherein said voltage reference circuit includes four diode-connected transistors connected in series between said gate of said fifth transistor and said reference-voltage pin.
Claim 5
Dependent Claim
12 words
The circuit of claim 3, wherein said diode-connected transistors are N-channel transistors.
Claim 6
Dependent Claim
23 words
The circuit of claim 1, wherein said second source-drain of said fifth transistor is coupled to said output through a Schmidt trigger circuit.
Claim 7
Dependent Claim
23 words
The circuit of claim 1, wherein said second source-drain of said fifth transistor is coupled to said reference voltage pin by a capacitor.
Claim 8
Dependent Claim
22 words
The circuit of claim 1, wherein said second source-drain of said fifth transistor is coupled to said reference-voltage pin by a resistor.
Claim 9
Dependent Claim
41 words
The circuit of claim 1 further including a sixth transistor, a gate of said sixth transistor coupled to said supply-voltage pin, a source-drain path of said sixth transistor coupled between said reference-voltage pin and said second source-drain of said fifth transistor.
Claim 10
Dependent Claim
58 words
The circuit of claim 1 further including a sixth transistor, a gate of said sixth transistor coupled to said supply-voltage pin, a source-drain path of said sixth transistor coupled between said reference-voltage pin and said second source-drain of said fifth transistor, the source-drain path of said sixth transistor being longer than the source-drain path of said fifth transistor.
Claim 11
Independent Claim
115 words
A method for providing high-voltage sensing at a signal pin of an integrated circuit, the method comprising the steps of: sensing to determine whether or not the voltage at said signal pin is greater than a reference voltage plus a first number of transistor threshold voltages; at the same time, sensing to determine whether or not said voltage at said signal pin is greater than the supply voltage plus a second number of transistor threshold voltages; and if said voltage at said signal pin is greater than both said reference voltage plus said first number of transistor threshold voltages and said supply voltage plus said second number of transistor threshold voltages, generating an output signal.
Claim 12
Independent Claim
115 words
A method for providing high-voltage sensing at a signal pin of an integrated circuit, the method comprising the steps of: sensing to determine whether or not the voltage at said signal pin is greater than a reference voltage plus a first number of transistor threshold voltages; at the same time, sensing to determine whether or not said voltage at said signal pin is greater than the supply voltage plus a second number of transistor threshold voltages; and if said voltage at said signal pin is greater than both said reference voltage plus said first number of transistor threshold voltages and said supply voltage plus said second number of transistor threshold voltages, generating an output signal.
Claim 13
Dependent Claim
20 words
The method of claim 10, wherein said reference voltage is the sum of a third number of transistor threshold voltages.
Claim 14
Dependent Claim
19 words
The method of claim 10, wherein said reference voltage is the sum of four transistor N-channel transistor threshold voltages.
Claim 15
Dependent Claim
15 words
The method of claim 10, wherein said transistor threshold voltages are P-channel transistor threshold voltages.
Claim 16
Dependent Claim
18 words
The method of claim 10, wherein said first number of transistor threshold voltages is two P-channel threshold voltages.
Claim 17
Dependent Claim
18 words
The method of claim 10, wherein said second number of transistor threshold voltages is two P-channel threshold voltages.
Claim 18
Dependent Claim
13 words
The method of claim 10, wherein said output signal is a high voltage.
Claim 19
Dependent Claim
247 words
The method of claim 10, wherein said signal pin is connected to a circuit, said circuit further including a Vcc pin and a Vss pin, said circuit comprising: a first transistor with a first source-drain a second source-drain and a gate, said first source-drain of said first transistor coupled to said signal pin; a second transistor with a first source-drain a second source-drain and a gate, said first source-drain of said second transistor coupled to said second source-drain of said first transistor, said gate of said second transistor coupled to said Vcc pin; a third transistor with a first source-drain a second source-drain and a gate, said first source-drain of said third transistor coupled to said signal pin, said gate of said third transistor coupled to said gate of said first transistor; a fourth transistor with a first source-drain a second source-drain and a gate, said first source-drain of said fourth transistor coupled to said second source-drain of said third transistor, said gate of said fourth transistor coupled to said gate of said second transistor; a fifth transistor with a first source-drain a second source-drain and a gate, said first source-drain of said fifth transistor coupled to said second source-drain of said fourth transistor; said second source-drain of said fifth transistor coupled to said output, said gate of said fifth transistor coupled to said second source-drain of said second transistor; and a voltage reference circuit coupled between said gate of said fifth transistor and said Vss pin.
Claim 20
Dependent Claim
20 words
The method of claim 17, wherein each of said first, second, third, fourth and fifth transistors is a P-channel transistor.
Claim 21
Dependent Claim
28 words
The method of claim 17, wherein said voltage reference circuit includes four diode-connected transistors connected in series between said gate of said fifth transistor and said Vss pin.
Claim 22
Dependent Claim
29 words
The method of claim 17, wherein said voltage reference circuit includes four N-channel diode-connected transistors connected in series between said gate of said fifth transistor and said Vss pin.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |