Computer system with a bus controller

Claim 1

A computer system comprising: a microprocessor providing address information and information about a start and type of its bus cycle; a memory: a latch for controllably latching said address information and for providing latched address information: a bus controller responsive to said bus cycle information and to a processor clock, for asserting a first signal indicating said address information provided by said microprocessor to be valid, wherein said first signal controls said latch so that: when said first signal is asserted, said latch latches said microprocessor address information; and when said first signal is deasserted, said latch is transparent to said microprocessor address information; and a memory control circuit having a first input for receiving said address information in an unlatched condition, a second input for receiving said first signal, and a third input for receiving said bus cycle information, said memory control circuit being responsive to signals at said first, second, and third inputs for providing a second signal for selectively enabling said memory, said memory control circuit further being responsive to the signal at said second input for latching said second signal.