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US5396289A Expired / Lapsed US ⏱️ 0.0 years remaining

Solid state imaging device

Assignee: Olympus Corp
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Filing: 1993-07-06
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Granted: 1995-03-07
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Expires: 2013-07-06
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Abstract

Abstract In a solid state imaging device having a group of pixels arrayed in the form of a matrix, after a vertical scanning circuit delivers a drive signal for one first switching element, a horizontal scanning circuit is driven to sequentially read out pixel signals from the respective pixels on one predetermined row line to a signal output line, and one second switching element connected to another row line, from which pixel signals have been read out one horizontal scanning period before the readout for the predetermined row line, is driven to reset the respective pixels connected to another said row line upon the driving of the horizontal scanning circuit. Both the readout and reset operations for the respective pixels are point-sequentially performed so that periods of time integrating the pixels at all the positions on the imaging device can be made equal to each other.

Inventors

  • 👤 Tsutomu Nakamura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 12:44
CPC Classifications
H; H04; H04N; H04N23/00; H04N23/70; H04N23/73; H04N25/00; H04N25/60; H04N25/62; H04N25/621; H04N25/622; H04N25/70; H04N25/76

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 399 words
A solid state charge modulation device type imaging device including, as pixel constituting elements, image sensors in each of which a source-drain current is modulated depending on an amount of electric charges produced under light irradiation and integrated below a gate electrode, and comprising: a pixel group prepared by arraying said pixels in the form of a matrix, a plurality of row lines to each of which are commonly connected sources of those pixels arrayed in the X-direction for each row, a plurality of column lines to each of which are commonly connected gates of those pixels arrayed in the Y-direction for each column, a horizontal scanning circuit for sequentially delivering a drive signal to said column lines, a vertical scanning circuit for delivering first, second and third signals to sequentially drive first switching elements through each of which said row lines are each connected to a signal output line, second switching elements through each of which said row lines are each connected to a reset line applied with reset potential, and third switching elements through each of which said row lines are each connected to an offset readout line, and means for delaying a readout signal over said signal output line by two horizontal scanning periods, and then outputting a differential signal between said delayed readout signal and a dark offset signal read out to said offset readout line, both said scanning circuits being arranged such that after said vertical scanning circuit delivers a drive signal for one of said first switching elements, said horizontal scanning circuit is driven to sequentially read out pixel signals from the respective pixels on one predetermined row line; one of said second switching elements connected to another row line, from which pixel signals have been read out one horizontal scanning period before the readout for said predetermined row line, is driven to sequentially reset the respective pixels connected to another said row line upon the driving of said horizontal scanning circuit; and one of said third switching elements connected to still another row line, from which pixel signals have been read out two horizontal scanning periods before the read for said predetermined row line, is driven to sequentially read out dark offset signals of the respective pixels connected to still another said row line upon the driving of said horizontal scanning circuit, wherein said pixel signals are non-destructively read out in real-time.
Claim 2
Dependent Claim 399 words
A solid state charge modulation device type imaging device including, as pixel constituting elements, image sensors in each of which a source-drain current is modulated depending on an amount of electric charges produced under light irradiation and integrated below a gate electrode, and comprising: a pixel group prepared by arraying said pixels in the form of a matrix, a plurality of row lines to each of which are commonly connected sources of those pixels arrayed in the X-direction for each row, a plurality of column lines to each of which are commonly connected gates of those pixels arrayed in the Y-direction for each column, a horizontal scanning circuit for sequentially delivering a drive signal to said column lines, a vertical scanning circuit for delivering first, second and third signals to sequentially drive first switching elements through each of which said row lines are each connected to a signal output line, second switching elements through each of which said row lines are each connected to a reset line applied with reset potential, and third switching elements through each of which said row lines are each connected to an offset readout line, and means for delaying a readout signal over said signal output line by two horizontal scanning periods, and then outputting a differential signal between said delayed readout signal and a dark offset signal read out to said offset readout line, both said scanning circuits being arranged such that after said vertical scanning circuit delivers a drive signal for one of said first switching elements, said horizontal scanning circuit is driven to sequentially read out pixel signals from the respective pixels on one predetermined row line; one of said second switching elements connected to another row line, from which pixel signals have been read out one horizontal scanning period before the readout for said predetermined row line, is driven to sequentially reset the respective pixels connected to another said row line upon the driving of said horizontal scanning circuit; and one of said third switching elements connected to still another row line, from which pixel signals have been read out two horizontal scanning periods before the read for said predetermined row line, is driven to sequentially read out dark offset signals of the respective pixels connected to still another said row line upon the driving of said horizontal scanning circuit, wherein said pixel signals are non-destructively read out in real-time.

References Cited (Backward Citations)

US4531156A Cited
US4700231A Cited
US4684992A Cited
US4929994A Cited
US4974008A Cited
US4862276A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-03-06 1998-09-05 1999-03-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-03-06 2002-09-05 2003-03-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-03-06 2006-09-05 2007-03-07 $7700.00 Window Closed / Lapsed

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