Patent US5396105A successfully refreshed from Google Patents.
US5396105A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Toshiba Corp
•
Filing: 1992-09-04
•
Granted: 1995-03-07
•
Expires: 2012-09-04
Abstract
Abstract A MOSFET constituting a flip-flop circuit and a MOSFET for control of reading and writing data out of and into a memory cell are formed on a semiconductor. The gate electrode of the first MOSFET and the gate electrode of the second MOSFET are formed by layers of different levels. The gate electrodes have an overlapped portion R. The first and second MOSFETs are arranged symmetrically with respect to a certain point P. By virtue of the above structure, the degree of integration of a static RAM is enhanced.
Inventors
- 👤 Takeo Nakayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:36
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/0144; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
247 words
A semiconductor device having a flip-flop circuit used as a memory cell in a static RAM, and a transfer gate for control of reading and writing data out of and into the memory cell, respectively, comprising: a flip-flop circuit having a first MOSFET with a gate electrode having first and second end portions, the gate electrode being formed by a layer of a first level; a transfer gate having a second MOSFET with a gate electrode formed by a layer of a second level different from the first level, one of the first and second end portions of the gate electrode of the first MOSFET being overlapped with the gate electrode of the second MOSFET; the flip-flop circuit having a third MOSFET with a gate electrode with first and second end portions, the gate electrode being formed by a layer of the first level; the transfer gate having a fourth MOSFET with a gate electrode formed by a layer of the second level, one of the first and second end portions of the gate electrode of the third MOSFET being overlapped with the gate electrode of the fourth MOSFET; the first, second, third and fourth MOSFETS each having a diffusion layer; and the other end portion of the gate electrode of the first MOSFET connected to diffusion layers of the third and fourth MOSFETs, and the other end portion of the gate electrode of the third MOSFET connected to diffusion layers of the first and second MOSFETs.
Claim 2
Dependent Claim
247 words
A semiconductor device having a flip-flop circuit used as a memory cell in a static RAM, and a transfer gate for control of reading and writing data out of and into the memory cell, respectively, comprising: a flip-flop circuit having a first MOSFET with a gate electrode having first and second end portions, the gate electrode being formed by a layer of a first level; a transfer gate having a second MOSFET with a gate electrode formed by a layer of a second level different from the first level, one of the first and second end portions of the gate electrode of the first MOSFET being overlapped with the gate electrode of the second MOSFET; the flip-flop circuit having a third MOSFET with a gate electrode with first and second end portions, the gate electrode being formed by a layer of the first level; the transfer gate having a fourth MOSFET with a gate electrode formed by a layer of the second level, one of the first and second end portions of the gate electrode of the third MOSFET being overlapped with the gate electrode of the fourth MOSFET; the first, second, third and fourth MOSFETS each having a diffusion layer; and the other end portion of the gate electrode of the first MOSFET connected to diffusion layers of the third and fourth MOSFETs, and the other end portion of the gate electrode of the third MOSFET connected to diffusion layers of the first and second MOSFETs.
Claim 3
Dependent Claim
71 words
The semiconductor device according to claim 1, wherein a gate insulating film of the first MOSFET has a thickness different from that of the second MOSFET, and the ratio of the gate capacitance of the first MOSFET to that of the second MOSFET is determined by the ratio of the thickness of the gate insulating film of the first MOSFET to that of a gate insulating film of the second MOSFET.
Claim 4
Dependent Claim
21 words
The semiconductor device according to claim 2, wherein the first MOSFET has a unit-area gate capacitance larger than the second MOSFET.
Claim 5
Dependent Claim
33 words
The semiconductor device according to claim 2, wherein the gate insulating film of the first MOSFET is made of a material different from that of the gate insulating film of the second MOSFET.
Claim 6
Dependent Claim
48 words
The semiconductor device according to claim 1, wherein the gate electrode of the first MOSFET is formed by one of a laminated film consisting of a polysilicon film and a high-fusing-point metal film, and a laminated film consisting of a polysilicon film and a high-fusing-point metal silicide film.
Claim 7
Dependent Claim
48 words
The semiconductor device according to claim 1, wherein the gate electrode of the second MOSFET is formed by one of a laminated film consisting of a polysilicon film and a high-fusing-point metal film, and a laminated film consisting of a polysilicon film and a high-fusing-point metal silicide film.
Claim 8
Dependent Claim
48 words
The semiconductor device according to claim 1, wherein a gate insulating film of the first MOSFET is formed by one of a SiO 2 film, a SiN film, a TaO film, a composite film consisting of a SiO 2 film, a SiN film, and a SiO 2 film.
Claim 9
Dependent Claim
48 words
The semiconductor device according to claim 1, wherein a gate insulating film of the second MOSFET is formed by one of a SiO 2 film, a SiN film, a TaO film, a composite film consisting of a SiO 2 film, a SiN film, and a SiO 2 film.
Claim 10
Dependent Claim
21 words
The semiconductor device according to claim 1, wherein the first to fourth MOSFETS are arranged symmetrically with to a certain point.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-06 | 1998-09-05 | 1999-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-06 | 2002-09-05 | 2003-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-06 | 2006-09-05 | 2007-03-07 | $7700.00 | Window Closed / Lapsed |