Patent US2626451A successfully refreshed from Google Patents.
Patent US5396102A successfully refreshed from Google Patents.
US5396102A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Hitachi Ltd
•
Filing: 1993-03-02
•
Granted: 1995-03-07
•
Expires: 2013-03-02
Abstract
Abstract In an SIP type module of the type wherein memory ICs are mounted to both surfaces of a substrate, the present invention provides a face package type memory module wherein packaging is made in an inclined direction in place of vertical packaging of the prior art technique and only the memory ICs mounted to the upper surface side of the substrate are deviated to the positions closer to the end portion of the substrate in order to drastically reduce the packaging height.
Inventors
- 👤 Sugano Toshio
- 👤 Tsukui Seiichirou
- 👤 Suzuki Shigeru
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:15
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/141; H01; H01R; H01R12/00; H01R12/70; H01R12/71; H01R12/72; H01R12/721; H10; H10W; H10W72/00; H10W90/00; H05K1/0286; H05K1/0287; H05K1/0289; H05K1/18; H05K1/181; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/0929; H05K2201/09336; H05K2201/10; H05K2201/10007; H05K2201/10159; H05K2201/10189; H05K2201/10431; H05K2201/10439; H05K2201/10484; H05K2201/10613; H05K2201/10621; H05K2201/10689; H05K2203/00; H05K2203/15; H05K2203/1572; H05K3/00; H05K3/36; H05K3/366; H10W70/00; H10W70/40; H10W70/60; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/884; H10W90/20
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
264 words
A semiconductor memory module to be mounted to a substrate, comprising: a substantially rectangular shaped double-sided board having a first surface, a second surface, a first side edge which is one of its longer side edges of the board to be mounted to said substrate and a second side edge which is opposite to said first side edge; first memory devices mounted on said first surface along and adjacent to said second side edge in a row, said first memory devices each having same number and same function of terminals including a first terminal and second terminals; and second memory devices mounted on said second surface along and adjacent to said second side edge in a row, said second memory devices each having same number and same function of terminals including a first terminal and second terminals, wherein said first terminal and second terminals of said second memory devices having same function as said first terminal and second terminals of said first memory devices, wherein said first terminals of said first memory devices are electrically connected to each other, said first terminals of said second memory devices are electrically connected to each other, and each of said second terminals of one of said first memory devices and each of said second terminals of one of said second memory of one of said second memory devices are electrically connected to each other, and wherein said second memory devices are arranged closer to said second side edge than said first memory devices, so as to mount said memory module at an acute angle with said substrate.
Claim 2
Dependent Claim
264 words
A semiconductor memory module to be mounted to a substrate, comprising: a substantially rectangular shaped double-sided board having a first surface, a second surface, a first side edge which is one of its longer side edges of the board to be mounted to said substrate and a second side edge which is opposite to said first side edge; first memory devices mounted on said first surface along and adjacent to said second side edge in a row, said first memory devices each having same number and same function of terminals including a first terminal and second terminals; and second memory devices mounted on said second surface along and adjacent to said second side edge in a row, said second memory devices each having same number and same function of terminals including a first terminal and second terminals, wherein said first terminal and second terminals of said second memory devices having same function as said first terminal and second terminals of said first memory devices, wherein said first terminals of said first memory devices are electrically connected to each other, said first terminals of said second memory devices are electrically connected to each other, and each of said second terminals of one of said first memory devices and each of said second terminals of one of said second memory of one of said second memory devices are electrically connected to each other, and wherein said second memory devices are arranged closer to said second side edge than said first memory devices, so as to mount said memory module at an acute angle with said substrate.
Claim 3
Dependent Claim
24 words
A semiconductor memory module according to claim 1, wherein each said first terminal of said first memory devices receives a row address strobe signal.
Claim 4
Dependent Claim
24 words
A semiconductor memory module according to claim 1, wherein each said first terminal of said second memory devices receives a row address strobe signal.
Claim 5
Dependent Claim
24 words
A semiconductor memory module according to claim 1, wherein each said second terminals of said first and second memory devices transmits data input/output signals.
Claim 6
Dependent Claim
39 words
A semiconductor memory module according to claim 1, wherein said terminals of said first and second memory devices each includes third terminals, and wherein each of said third terminals of said first and second memory devices are electrically connected.
Claim 7
Dependent Claim
23 words
A semiconductor memory module according to claim 5, wherein each said third terminals of said first and second memory devices receives address signal.
Claim 8
Dependent Claim
29 words
A semiconductor memory module according to claim 1, wherein said double-sided board is mounted to said substrate at said acute angle with said second surface facing toward said substrate.
References Cited (Backward Citations)
US4074342A
Cited
US4616655A
Cited
US4994896A
Cited
US4982265A
Cited
US5061990A
Cited
US4984064A
Cited
US5103247A
Cited
US5227664A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-06 | 1998-09-05 | 1999-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-06 | 2002-09-05 | 2003-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-06 | 2006-09-05 | 2007-03-07 | $7700.00 | Window Closed / Lapsed |