Patent US5395797A successfully refreshed from Google Patents.
US5395797A
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Antifuse structure and method of fabrication
Assignee: Texas Instruments Inc
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Filing: 1993-11-12
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Granted: 1995-03-07
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Expires: 2013-11-12
Abstract
Abstract An antifuse structure (20) and method of fabrication are provided. A first conductive layer (A) is etched according to a first mask (62a) having a first pattern and according to a second mask (64a) having a second pattern. A first insulative layer (30) is disposed over the first conductive layer (A) and etched according to a third mask (40a) having a third pattern to expose at least one section of the first conductive layer (A). A second insulative layer (26) is disposed adjacent at least one exposed section of the first conductive layer (A). A second conductive layer (1) is disposed over the second insulative layer (26) so that the antifuse structure (20) includes at least one antifuse region (A1) where a section of the second insulative layer (26) is adjacent the first (A) and second (1) conductive layers. The antifuse region (A1) has a sublithographic vertical dimension (t) according to a thickness of the first conductive layer (A). Further, the antifuse region (A1) has a sublithographic horizontal dimension (L) according to an overlap between the first (62a) and second (64a) masks.
Inventors
- 👤 Kueing-Long Chen
- 👤 Ashwin H. Shah
- 👤 David K. Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:00
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; Y; Y10; Y10S; Y10S148/00; Y10S148/055; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
167 words
A method of fabricating an antifuse structure, comprising the steps of: depositing a first conductive layer; etching said first conductive layer according to a first mask having a first pattern; etching said first conductive layer according to a second mask having a second pattern; forming a first insulative layer over said first conductive layer; etching said first insulative layer according to a third mask having a third pattern to expose at least one section of said first conductive layer; forming a second insulative layer adjacent at least one said exposed section of said first conductive layer; and depositing a second conductive layer over said second insulative layer so that the antifuse structure includes at least one antifuse region where a section of said second insulative layer is adjacent said first and second conductive layers, said antifuse region having a sublithographic vertical dimension according to a thickness of said first conductive layer and having a sublithographic horizontal dimension according to an overlap between said first and second masks.
Claim 2
Independent Claim
167 words
A method of fabricating an antifuse structure, comprising the steps of: depositing a first conductive layer; etching said first conductive layer according to a first mask having a first pattern; etching said first conductive layer according to a second mask having a second pattern; forming a first insulative layer over said first conductive layer; etching said first insulative layer according to a third mask having a third pattern to expose at least one section of said first conductive layer; forming a second insulative layer adjacent at least one said exposed section of said first conductive layer; and depositing a second conductive layer over said second insulative layer so that the antifuse structure includes at least one antifuse region where a section of said second insulative layer is adjacent said first and second conductive layers, said antifuse region having a sublithographic vertical dimension according to a thickness of said first conductive layer and having a sublithographic horizontal dimension according to an overlap between said first and second masks.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein said step of etching said first insulative layer comprises the step of etching said first conductive layer.
Claim 4
Dependent Claim
27 words
The method of claim 1 wherein said step of etching said first insulative layer comprises the step of etching an antifuse window in said first insulative layer.
Claim 5
Dependent Claim
35 words
The method of claim 3 wherein said antifuse window etching step comprises the step of etching said antifuse window in said first insulative layer so that multiple antifuse regions are situated in said antifuse window.
Claim 6
Dependent Claim
26 words
The method of claim 1 wherein said step of etching said first insulative layer comprises the step of etching a slot in said first insulative layer.
Claim 7
Dependent Claim
22 words
The method of claim 1 wherein said step of depositing said first conductive layer comprises the step of depositing a polysilicon layer.
Claim 8
Dependent Claim
20 words
The method of claim 1 and further comprising the step of implanting and annealing dopants in said first conductive layer.
Claim 9
Dependent Claim
23 words
The method of claim 1 and further comprising the step of programming said antifuse region to connect said first and second conductive layers.
Claim 10
Dependent Claim
27 words
The method of claim 8 wherein said programming step comprises the step of applying a programming voltage between said first conductive layer and said second conductive layer.
Claim 11
Dependent Claim
22 words
The method of claim 8 wherein said programming step comprises the step of melting said second insulative layer in said antifuse region.
Claim 12
Independent Claim
158 words
A method of fabricating an antifuse structure, comprising the steps of: depositing a first conductive layer; etching said first conductive layer according to a first mask having a first pattern; forming a first insulative layer over said first conductive layer; etching said first insulative layer according to a second mask having a second pattern to expose at least one section of said first conductive layer; forming a second insulative layer adjacent at least one said exposed section of said first conductive layer; and depositing a second conductive layer over said second insulative layer so that the antifuse structure includes at least one antifuse region where a section of said second insulative layer is adjacent said first and second conductive layers, said antifuse region having a sublithographic vertical dimension according to a thickness of said first conductive layer and having a sublithographic horizontal dimension according to an offset of said second conductive layer relative to said first conductive layer.
Claim 13
Independent Claim
158 words
A method of fabricating an antifuse structure, comprising the steps of: depositing a first conductive layer; etching said first conductive layer according to a first mask having a first pattern; forming a first insulative layer over said first conductive layer; etching said first insulative layer according to a second mask having a second pattern to expose at least one section of said first conductive layer; forming a second insulative layer adjacent at least one said exposed section of said first conductive layer; and depositing a second conductive layer over said second insulative layer so that the antifuse structure includes at least one antifuse region where a section of said second insulative layer is adjacent said first and second conductive layers, said antifuse region having a sublithographic vertical dimension according to a thickness of said first conductive layer and having a sublithographic horizontal dimension according to an offset of said second conductive layer relative to said first conductive layer.
Claim 14
Dependent Claim
59 words
The method of claim 11 and further comprising the step of etching said second conductive layer to form a plurality of second lines, so that the antifuse structure includes a plurality of antifuse regions each having an associated sublithographic horizontal dimension according to an offset of an associated one of said second lines relative to said first conductive layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-06 | 1998-09-05 | 1999-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-06 | 2002-09-05 | 2003-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-06 | 2006-09-05 | 2007-03-07 | $7700.00 | Window Closed / Lapsed |