Page printer controller including a single chip superscalar microprocessor with graphics functional units

Claim 1

A printer controller comprising: a single chip superscalar microprocessor, having a bidirectional data bus interface, a bidirectional Input/Output (I/O) bus interface, and an address bus interface, said superscalar microprocessor comprising, 1) an instruction processor having an instruction scheduler for issuing instructions to a plurality of functional units, said scheduler coupled to said plurality of functional units and operable to issue instructions in parallel to said plurality of functional units, and said plurality of functional units includes an orthogonal rotator unit, a bit/byte mirror unit, and a pixel modification unit; 2) a printer video processor for generating a plurality of control signals for a printer engine, for generating memory addresses of data to be fetched, and for serializing fetched data and providing serialized data to said printer engine, said printer video processor having an adder, a constants ROM, a register file, a command register, a mode register, a status register and a video port; 3) a data cache and an instruction cache, each of said caches coupled to said instruction processor; 4) an I/O controller, coupled to said I/O bus interface, and said I/O bus interface coupled to an I/O bus external to said superscalar microprocessor; 5) a memory controller for receiving memory transaction requests from said I/O controller, said printer video processor, said data cache, and said instruction cache, said memory controller coupled to said printer video processor, said data cache, said instruction cache, said data bus interface, said address bus interface and said I/O bus interface; wherein said instruction processor accesses printer video processor register file through said memory controller and sad I/O controller having write access to said data bus interface through said memory controller.