Patent US5394337A successfully refreshed from Google Patents.
US5394337A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for wire routing of a semiconductor integrated circuit and apparatus for implementing the same
Assignee: NEC Corp
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Filing: 1992-10-23
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Granted: 1995-02-28
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Expires: 2012-10-23
Abstract
Abstract A method and apparatus for wire routing of a semiconductor integrated circuit wherein the interconnection between the functional blocks disposed on a chip of the semiconductor integrated circuit having four or more wiring layers is implemented by computers. A plurality of adjacent wiring layers form a single set, and for at least two sets, the wire routing between terminals of the functional blocks lying on the wiring layers formed by the sets is carried out for each set independently from the other set. A plurality of computers are used, which communicate with each other through their network. A file system of one computer is shared between the two computers so that the wire routing process program, input information on the wire routing and a wire routing result can be stored within the shared file system, whereby an efficient concurrent processing is possible and the processing speed can be improved while the number of wiring layers dealt with by each wire routing process are reduced.
Inventors
- 👤 Keisuke Shinjo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:11
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/394
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
80 words
Method for wire routing of a semiconductor integrated circuit having functional blocks disposed on a chip, four or more wiring layers, and terminals of said blocks lying on said wiring layers, the method comprising the steps of: (a) providing in said integrated circuit a plurality of sets of adjacent wiring layers; (b) providing at least one computer; and (c) carrying out the wire routing between the terminals of the blocks for a plurality of said sets concurrently by said computer.
Claim 2
Dependent Claim
80 words
Method for wire routing of a semiconductor integrated circuit having functional blocks disposed on a chip, four or more wiring layers, and terminals of said blocks lying on said wiring layers, the method comprising the steps of: (a) providing in said integrated circuit a plurality of sets of adjacent wiring layers; (b) providing at least one computer; and (c) carrying out the wire routing between the terminals of the blocks for a plurality of said sets concurrently by said computer.
Claim 3
Dependent Claim
100 words
Method for wire routing of a semiconductor integrated circuit as set forth in claim 1, wherein said carrying out step comprises a first wire routing process for connecting between the terminal of a functional block lying on a first wiring layer and the terminal of a functional block lying on a second wiring layer adjacent to said first wiring layer and a second wire routing process for connecting between the terminal of a functional block lying on a third wiring layer and the terminal of a functional block lying on a fourth wiring layer adjacent to said third wiring layer.
Claim 4
Dependent Claim
82 words
Method for wire routing of a semiconductor integrated circuit as set forth in claim 1 wherein a plurality of computers are used and communicate with each other through a network thereof, and at least one file system possessed by at least one of the computers is shared by at least two of the computers so that a wire routing process program of the semiconductor integrated circuit, an input information on the wire routing process and a wire routing result are stored therein.
Claim 5
Dependent Claim
33 words
Method for wire routing of a semiconductor integrated circuit as set forth in claim 3 wherein the wire routing process for each set of wiring layers is concurrently carried out by independent computers.
Claim 6
Dependent Claim
44 words
Method for wire routing of a semiconductor integrated circuit as set forth in claim 1 wherein said computer comprises a plurality of independent arithmetic operation units to concurrently execute a wire routing process for each set of wiring layers by said arithmetic operation units.
Claim 7
Dependent Claim
135 words
Apparatus for wire routing of a semiconductor integrated circuit including functional blocks disposed on a chip of the semiconductor integrated circuit, and four or more wiring layers for interconnection between the functional blocks, said apparatus comprising at least two arithmetic operation units and at least one file system, each arithmetic operation unit carrying out the wire routing between terminals of the functional blocks lying on the wiring layers formed by one set of a plurality of adjacent wiring layers independently of another arithmetic operation unit for another set of a plurality of adjacent wiring layers, said file system storing a wire routing process program of the semiconductor integrated circuit, an input information on the wire routing and a wire routing process result, said file system being connected to said at least two arithmetic operation units.
Claim 8
Dependent Claim
135 words
Apparatus for wire routing of a semiconductor integrated circuit including functional blocks disposed on a chip of the semiconductor integrated circuit, and four or more wiring layers for interconnection between the functional blocks, said apparatus comprising at least two arithmetic operation units and at least one file system, each arithmetic operation unit carrying out the wire routing between terminals of the functional blocks lying on the wiring layers formed by one set of a plurality of adjacent wiring layers independently of another arithmetic operation unit for another set of a plurality of adjacent wiring layers, said file system storing a wire routing process program of the semiconductor integrated circuit, an input information on the wire routing and a wire routing process result, said file system being connected to said at least two arithmetic operation units.
Claim 9
Dependent Claim
152 words
Apparatus for wire routing of a semiconductor integrated circuit in which an interconnection between functional blocks disposed on a chip of the semiconductor integrated circuit is comprised of four or more wiring layers, said apparatus comprising at least two computers, each of said computers including an arithmetic operation unit and at least one file system, said arithmetic operation unit of each computer carrying out a wire routing between terminals of the functional blocks lying on the wiring layers formed by a set of a plurality of adjacent wiring layers independently of the arithmetic operation unit of another computer for another set of a plurality of adjacent wiring layers, said file system of at least one computer storing a wire routing process program of the semiconductor integrated circuit, an input information on the wire routing and a wire routing result and being connected to at least one arithmetic operation unit of another computer.
Claim 10
Dependent Claim
152 words
Apparatus for wire routing of a semiconductor integrated circuit in which an interconnection between functional blocks disposed on a chip of the semiconductor integrated circuit is comprised of four or more wiring layers, said apparatus comprising at least two computers, each of said computers including an arithmetic operation unit and at least one file system, said arithmetic operation unit of each computer carrying out a wire routing between terminals of the functional blocks lying on the wiring layers formed by a set of a plurality of adjacent wiring layers independently of the arithmetic operation unit of another computer for another set of a plurality of adjacent wiring layers, said file system of at least one computer storing a wire routing process program of the semiconductor integrated circuit, an input information on the wire routing and a wire routing result and being connected to at least one arithmetic operation unit of another computer.
References Cited (Backward Citations)
US4823276A
Cited
US4791609A
Cited
US4910680A
Cited
US5062054A
Cited
US5124273A
Cited
US5121336A
Cited
US4979018A
Cited
US5229629A
Cited
US5196362A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |