US5394294A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self protective decoupling capacitor structure
Assignee: International Business Machines Corp
•
Filing: 1992-12-17
•
Granted: 1995-02-28
•
Expires: 2012-12-17
Abstract
Abstract An integrated circuit decoupling capacitor is divided into a plurality of discrete segments. The segments are connected electrically in parallel and are redundant to an extent that if one segment (or if desired more than one segment) fails, the remaining segments have sufficient capacitance to provide the required decoupling function. Each decoupling capacitor segment has a fuse connected in series with it. The fuse opens in response to a fault in a decoupling capacitor segment that would otherwise cause that segment to short the power supply to ground.
Inventors
- 👤 Shaw-Ning Mei
- 👤 Dominic J. Schepis
- 👤 Andrie S. Yapsir
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/212; H10D89/00; H10D89/211; H10D89/213
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
122 words
A decoupling capacitor formed in a semiconductor substrate to protect a logic circuit formed in said semiconductor substrate from rapid changes in power supply voltage connected to said logic circuit, said decoupling capacitor comprising in combination: an isolated, heavily doped region formed in said substrate, said heavily doped region extending to a top surface of said semiconductor substrate; a thin insulating layer formed on the top surface of said semiconductor substrate overlying said heavily doped region; a resistive layer formed on said thin insulating layer, said resistive layer patterned into a plurality of discrete capacitor plates each with an integral narrow fuse link formed of said resistive layer for coupling each of said plurality discrete capacitor plates to said power supply voltage.
Claim 2
Dependent Claim
122 words
A decoupling capacitor formed in a semiconductor substrate to protect a logic circuit formed in said semiconductor substrate from rapid changes in power supply voltage connected to said logic circuit, said decoupling capacitor comprising in combination: an isolated, heavily doped region formed in said substrate, said heavily doped region extending to a top surface of said semiconductor substrate; a thin insulating layer formed on the top surface of said semiconductor substrate overlying said heavily doped region; a resistive layer formed on said thin insulating layer, said resistive layer patterned into a plurality of discrete capacitor plates each with an integral narrow fuse link formed of said resistive layer for coupling each of said plurality discrete capacitor plates to said power supply voltage.
Claim 3
Dependent Claim
31 words
An integrated circuit decoupling capacitor as in claim 1, wherein each fuse links is on the order of 300 Å to 500 Å thick and 0.5 microns to 3.0 microns wide.
Claim 4
Dependent Claim
128 words
A decoupling capacitor formed in a semiconductor substrate to protect a logic circuit formed in said semiconductor substrate from rapid changes in power supply voltage connected to said logic circuit, said decoupling capacitor comprising in combination: an isolated, heavily doped region formed in said substrate, said heavily doped region extending to a top surface of said semiconductor substrate; a thin insulating layer formed on the top surface of said semiconductor substrate overlying said heavily doped region; a refractory metal silicide layer formed on said thin insulating layer, said refractory metal silicide layer patterned into a plurality of discrete capacitor plates each with an integral narrow fuse link formed of said refractory metal silicide layer for coupling each of said plurality discrete capacitor plates to said power supply voltage.
Claim 5
Dependent Claim
128 words
A decoupling capacitor formed in a semiconductor substrate to protect a logic circuit formed in said semiconductor substrate from rapid changes in power supply voltage connected to said logic circuit, said decoupling capacitor comprising in combination: an isolated, heavily doped region formed in said substrate, said heavily doped region extending to a top surface of said semiconductor substrate; a thin insulating layer formed on the top surface of said semiconductor substrate overlying said heavily doped region; a refractory metal silicide layer formed on said thin insulating layer, said refractory metal silicide layer patterned into a plurality of discrete capacitor plates each with an integral narrow fuse link formed of said refractory metal silicide layer for coupling each of said plurality discrete capacitor plates to said power supply voltage.
Claim 6
Dependent Claim
31 words
An integrated circuit decoupling capacitor as in claim 2, wherein each fuse links is on the order of 300 Å to 500 Å thick and 0.5 microns to 3.0 microns wide.
Claim 7
Dependent Claim
125 words
A decoupling capacitor formed in a semiconductor substrate to protect a logic circuit formed in said semiconductor substrate from rapid changes in power supply voltage connected to said logic circuit, said decoupling capacitor comprising in combination: an isolated, heavily doped region formed in said substrate, said heavily doped region extending to a top surface of said semiconductor substrate; a thin insulating layer formed on the top surface of said semiconductor substrate overlying said heavily doped region; a refractory metal layer formed on said thin insulating layer, said refractory metal layer patterned into a plurality of discrete capacitor plates each with an integral narrow fuse link formed of said refractory metal layer for coupling each of said plurality discrete capacitor plates to said power supply voltage.
Claim 8
Dependent Claim
125 words
A decoupling capacitor formed in a semiconductor substrate to protect a logic circuit formed in said semiconductor substrate from rapid changes in power supply voltage connected to said logic circuit, said decoupling capacitor comprising in combination: an isolated, heavily doped region formed in said substrate, said heavily doped region extending to a top surface of said semiconductor substrate; a thin insulating layer formed on the top surface of said semiconductor substrate overlying said heavily doped region; a refractory metal layer formed on said thin insulating layer, said refractory metal layer patterned into a plurality of discrete capacitor plates each with an integral narrow fuse link formed of said refractory metal layer for coupling each of said plurality discrete capacitor plates to said power supply voltage.
Claim 9
Dependent Claim
31 words
An integrated circuit decoupling capacitor as in claim 3, wherein each fuse links is on the order of 300 Å to 500 Å thick and 0.5 microns to 3.0 microns wide.
Claim 10
Dependent Claim
134 words
A decoupling capacitor formed in a semiconductor substrate to protect a logic circuit formed in said semiconductor substrate from rapid changes in power supply voltage connected to said logic circuit, said decoupling capacitor comprising in combination: an isolated, heavily doped region formed in said substrate, said heavily doped region extending to a top surface of said semiconductor substrate; a thin insulating layer formed on the top surface of said semiconductor substrate overlying said heavily doped region; a titanium silicide (TiSi 2 ) layer formed on said thin insulating layer, said titanium silicide (TiSi 2 ) layer patterned into a plurality of discrete capacitor plates each with an integral narrow fuse link formed of said titanium silicide (TiSi 2 ) layer for coupling each of said plurality discrete capacitor plates to said power supply voltage.
Claim 11
Dependent Claim
134 words
A decoupling capacitor formed in a semiconductor substrate to protect a logic circuit formed in said semiconductor substrate from rapid changes in power supply voltage connected to said logic circuit, said decoupling capacitor comprising in combination: an isolated, heavily doped region formed in said substrate, said heavily doped region extending to a top surface of said semiconductor substrate; a thin insulating layer formed on the top surface of said semiconductor substrate overlying said heavily doped region; a titanium silicide (TiSi 2 ) layer formed on said thin insulating layer, said titanium silicide (TiSi 2 ) layer patterned into a plurality of discrete capacitor plates each with an integral narrow fuse link formed of said titanium silicide (TiSi 2 ) layer for coupling each of said plurality discrete capacitor plates to said power supply voltage.
References Cited (Backward Citations)
US1842374A
Cited
US2216558A
Cited
US3303400A
Cited
US3772097A
Cited
US3769105A
Cited
US3619725A
Cited
US4553050A
Cited
US5031006A
Cited
US4720772A
Cited
US4757423A
Cited
US4680670A
Cited
US4945399A
Cited
US4894746A
Cited
US5032892A
Cited
US5050043A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |