← Back to Patent Explorer
US4553050A Expired / Lapsed US ⏱️ 0.0 years remaining

Transmission line terminator-decoupling capacitor chip for off-chip driver

Assignee: International Business Machines Corp
•
Filing: 1983-12-27
•
Granted: 1985-11-12
•
Expires: 2003-12-27
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A signal transmission line terminator for an off-chip driver circuit is disclosed in which each capacitor and resistor comprising each terminator are formed on the same chip separate from the driver circuit chip. The close proximity of the elements of the terminator reduce the path lengths therebetween to a minimum. The structure substantially eliminates the corresponding inductive reactance and concommitant ΔI noise at high switching rates employed in high performance computers.

Inventors

  • 👤 Irving Feinberg
  • 👤 Leon L. Wu
  • 👤 Leo Yuan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 17:10
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H10; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/206; H10W; H10W20/00; H10W20/40; H10W20/495; H10W20/496

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 192 words
A signal line terminator for a driver circuit energized by at least one source of voltage relative to ground and formed on a first semiconductor chip, said terminator comprising: one capacitor for each said voltage source and at least one resistor formed on a second chip, said first and second chips being connected to each other, one terminal of said resistor and one terminal of each said capacitor being connected to said ground, the other terminal of said resistor being connected to said driver circuit, the other terminal of each said capacitor being connected to a respective one of said at least one voltage source, said resistor being formed of a doped region of one conductivity type in said second chip and covered by a first dielectric layer apertured to provide first and a second conductive contacts to said region, and each said capacitor being formed of a first conductive layer on the upper surface of said first dielectric layer and a respective second conductive layer spaced from said first layer by a second dielectric layer, said first conductive layer and one of said contacts being connected together and to said ground.
Claim 2
Dependent Claim 192 words
A signal line terminator for a driver circuit energized by at least one source of voltage relative to ground and formed on a first semiconductor chip, said terminator comprising: one capacitor for each said voltage source and at least one resistor formed on a second chip, said first and second chips being connected to each other, one terminal of said resistor and one terminal of each said capacitor being connected to said ground, the other terminal of said resistor being connected to said driver circuit, the other terminal of each said capacitor being connected to a respective one of said at least one voltage source, said resistor being formed of a doped region of one conductivity type in said second chip and covered by a first dielectric layer apertured to provide first and a second conductive contacts to said region, and each said capacitor being formed of a first conductive layer on the upper surface of said first dielectric layer and a respective second conductive layer spaced from said first layer by a second dielectric layer, said first conductive layer and one of said contacts being connected together and to said ground.
Claim 3
Dependent Claim 14 words
The terminator defined in claim 1 wherein said second chip is a semiconductor chip.
Claim 4
Dependent Claim 21 words
The terminator defined in claim 1 wherein said first and second chips are mounted on and connected together via a module.
Claim 5
Dependent Claim 21 words
The terminator defined in claim 1 wherein said driver circuit is a push-pull driver circuit energized by two sources of voltage.
Claim 6
Dependent Claim 15 words
The terminator defined in claim 4 wherein two capacitors are formed on said second chip.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-11-11 1989-05-13 1989-11-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-11-11 1993-05-13 1993-11-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-11-11 1997-05-13 1997-11-12 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag