US3751682A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulsed voltage driver for capacitive load
Assignee: Unisys Corp
•
Filing: 1971-12-17
•
Granted: 1973-08-07
•
Expires: 1991-12-17
Abstract
Abstract A voltage source of pulsed signals for charging or discharging a capacitive load is disclosed. The circuit includes two complementary transistors serially coupled along their output (collector and emitter) electrodes between the two voltage sources as a push-pull driver. Their input (base) electrodes are each coupled in parallel by a respectively associated serially aligned capacitor and resistor to an input terminal that is driven by a binary logic level circuit while their common coupled output (collector) electrodes are coupled to a capacitive load.
Inventors
- 👤 J Howe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:10
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666; H03K17/667; H03K5/00; H03K5/01; H03K5/02
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
184 words
A capacitively loaded voltage driver, comprising: first and second complementary transistors, each having collector, emitter and base electrodes; first means for intercoupling the collector electrodes of said first and second transistors for forming an output terminal; second means for coupling the emitter electrode of said first transistor to a first voltage source; third means for coupling the emitter electrode of said second transistor to a second voltage source; fourth means for serially intercoupling a first capacitor means and a first resistor means between an input terminal and the base electrode of said first transistor; fifth means for serially intercoupling a second capacitor means and a second resistor means between said input terminal and the base electrode of said second transistor; sixth means for coupling said input terminal to a third voltage source; third resistor means for intercoupling the base and emitter electrodes of said first transistor; fourth resistor means for intercoupling the base and emitter electrodes of said second transistor; and, fifth resistor means for coupling the intercoupled collector electrodes of said first and second transistors to the emitter electrode of said first transistor.
Claim 2
Dependent Claim
184 words
A capacitively loaded voltage driver, comprising: first and second complementary transistors, each having collector, emitter and base electrodes; first means for intercoupling the collector electrodes of said first and second transistors for forming an output terminal; second means for coupling the emitter electrode of said first transistor to a first voltage source; third means for coupling the emitter electrode of said second transistor to a second voltage source; fourth means for serially intercoupling a first capacitor means and a first resistor means between an input terminal and the base electrode of said first transistor; fifth means for serially intercoupling a second capacitor means and a second resistor means between said input terminal and the base electrode of said second transistor; sixth means for coupling said input terminal to a third voltage source; third resistor means for intercoupling the base and emitter electrodes of said first transistor; fourth resistor means for intercoupling the base and emitter electrodes of said second transistor; and, fifth resistor means for coupling the intercoupled collector electrodes of said first and second transistors to the emitter electrode of said first transistor.
Claim 3
Dependent Claim
27 words
The driver of claim 1 wherein said first means includes a sixth resistor means for coupling the collector electrode of said first transistor to said output terminal.
Claim 4
Dependent Claim
27 words
The driver of claim 2 wherein said first means includes a seventh resistor means for coupling the collector electrode of said second transistor to said output terminal.
Claim 5
Dependent Claim
22 words
The driver of claim 1 wherein said first, second and third means are direct coupling means not including any discrete circuit components.
Claim 6
Dependent Claim
19 words
The driver of claim 1 wherein said first means are direct coupling means not including any discrete circuit components.
Claim 7
Dependent Claim
13 words
The driver of claim 1 wherein said sixth means includes an eighth resistor.
Claim 8
Dependent Claim
352 words
A capacitively loaded voltage driver, comprising: first and second complementary transistors, each having collector, emitter and base electrodes; first means for intercoupling the collector electrodes of said first and second transistors for forming an output terminal; second means for coupling the emitter electrode of said first transistor to a first voltage source; third means for coupling the emitter electrode of said second transistor to a second voltage source; fourth means for serially intercoupling a first capacitor means and a first resistor means between an input terminal and the base electrode of said first transistor; fifth means for serially intercoupling a second capacitor means and a second resistor means between said input terminal and the base electrode of said second transistor; sixth means for coupling said input terminal to a third voltage source; third resistor means for intercoupling the base and emitter electrodes of said first transistor; fourth resistor means for intercoupling the base and emitter electrodes of said second transistor; input circuit means coupled to said input terminal for normally coupling thereto a first input signal of a constant potential level and alternatively coupling thereto a second input signal of a constant potential level different than that of said first input signal and having relatiVely sharp leading and trailing edges and a given duration; said first and second capacitor means blocking DC current flow from said third voltage source to the base electrodes of said first and second transistors, respectively, for causing said first and second transistors to be normally held OFF; said second input signal leading edge being capacitively coupled to the bases of said first and second transistors by said first and second capacitors, respectively, for holding said second transistor OFF and turning said first transistor ON for a time less than the duration of said second input signal; said second input signal trailing edge being capacitively coupled to the bases of said first and second transistors by said first and second capacitors, respectively, for holding said first transistor OFF and turning said second transistor ON for a time less than the duration between successive ones of said input signal.
Claim 9
Dependent Claim
352 words
A capacitively loaded voltage driver, comprising: first and second complementary transistors, each having collector, emitter and base electrodes; first means for intercoupling the collector electrodes of said first and second transistors for forming an output terminal; second means for coupling the emitter electrode of said first transistor to a first voltage source; third means for coupling the emitter electrode of said second transistor to a second voltage source; fourth means for serially intercoupling a first capacitor means and a first resistor means between an input terminal and the base electrode of said first transistor; fifth means for serially intercoupling a second capacitor means and a second resistor means between said input terminal and the base electrode of said second transistor; sixth means for coupling said input terminal to a third voltage source; third resistor means for intercoupling the base and emitter electrodes of said first transistor; fourth resistor means for intercoupling the base and emitter electrodes of said second transistor; input circuit means coupled to said input terminal for normally coupling thereto a first input signal of a constant potential level and alternatively coupling thereto a second input signal of a constant potential level different than that of said first input signal and having relatiVely sharp leading and trailing edges and a given duration; said first and second capacitor means blocking DC current flow from said third voltage source to the base electrodes of said first and second transistors, respectively, for causing said first and second transistors to be normally held OFF; said second input signal leading edge being capacitively coupled to the bases of said first and second transistors by said first and second capacitors, respectively, for holding said second transistor OFF and turning said first transistor ON for a time less than the duration of said second input signal; said second input signal trailing edge being capacitively coupled to the bases of said first and second transistors by said first and second capacitors, respectively, for holding said first transistor OFF and turning said second transistor ON for a time less than the duration between successive ones of said input signal.
Claim 10
Dependent Claim
31 words
The driver of claim 8 further including a fifth resistor means for coupling the intercoupled collector electrodes of said first and second transistors to the emitter electrode of said first transistor.
Claim 11
Dependent Claim
27 words
The driver of claim 9 wherein said first means includes a sixth resistor means for coupling the collector electrode of said first transistor to said output terminal.
Claim 12
Dependent Claim
27 words
The driver of claim 10 wherein said first means includes a seventh resistor means for coupling the collector electrode of said second transistor to said output terminal.
Claim 13
Dependent Claim
22 words
The driver of claim 8 wherein said first, second and third means are direct coupling means not including any discrete circuit components.
Claim 14
Dependent Claim
19 words
The driver of claim 8 wherein said first means are direct coupling means not including any discrete circuit components.
Claim 15
Dependent Claim
13 words
The driver of claim 8 wherein said sixth means includes an eighth resistor.
References Cited (Backward Citations)
US3125694A
Cited
US2930942A
Cited
US2997606A
Cited
US3155963A
Cited
US3157797A
Cited
US3160766A
Cited
US3591858A
Cited
US3649851A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-06 | 1977-02-05 | 1977-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-06 | 1981-02-05 | 1981-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-06 | 1985-02-05 | 1985-08-07 | $7700.00 | Window Closed / Lapsed |