Patent US5394033A successfully refreshed from Google Patents.
US5394033A
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Structure and method for implementing hierarchical routing pools in a programmable logic circuit
Assignee: Lattice Semiconductor Corp
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Filing: 1993-09-01
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Granted: 1995-02-28
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Expires: 2013-09-01
Abstract
Abstract A programmable logic device has multiple groups of generic logic blocks. Each group of generic logic blocks is interconnected by a local routing pools. A global routing pool is provided to interconnect the local routing pools. The global and local routing pools can be implemented in volatile or non-volatile technology, such as E 2 PROM technology. The programmable logic device can also be implemented as an in-system programmable logic device.
Inventors
- 👤 Cyrus Y. Tsui
- 👤 Ju Shen
- 👤 Chanchi J. Cheng
- 👤 Ming C. Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
116 words
In a complex PLD, a programmable interconnection system for interconnecting programmable logic blocks comprising: a first programmable interconnection circuit for interconnecting a first group of programmable logic blocks, said first programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said first group; a second programmable interconnection circuit for interconnecting a second group of programmable logic blocks, said second group of programmable logic blocks being separate and distinct from said first group of programmable logic blocks, said second programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said second group; and a third programmable interconnection circuit for interconnecting said first and second programmable interconnection circuits.
Claim 2
Dependent Claim
116 words
In a complex PLD, a programmable interconnection system for interconnecting programmable logic blocks comprising: a first programmable interconnection circuit for interconnecting a first group of programmable logic blocks, said first programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said first group; a second programmable interconnection circuit for interconnecting a second group of programmable logic blocks, said second group of programmable logic blocks being separate and distinct from said first group of programmable logic blocks, said second programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said second group; and a third programmable interconnection circuit for interconnecting said first and second programmable interconnection circuits.
Claim 3
Dependent Claim
23 words
A programmable interconnection system as in claim 1, wherein said first, second and third interconnection circuits are implemented in a volatile memory technology.
Claim 4
Dependent Claim
23 words
A programmable interconnection system as in claim 1, wherein said first, second and third interconnection circuits are implemented in a non-volatile memory technology.
Claim 5
Dependent Claim
19 words
A programmable interconnection system as in claim 1, wherein said programmable interconenction system is reprogrammable using in-system programmable techniques.
Claim 6
Dependent Claim
108 words
A programmable interconnection system as in claim 1, wherein said programmable interconnection system being implemented in a programmable logic device having a plurality of input pins, said programmable logic blocks each having a plurality of input terminals and a plurlaity of output terminals, said first and second interconnection circuits each comprising: a first set of input terminals receiving signals from said output terminals of said programmable logic blocks; a second set of input terminals receiving signals from said input pins; and a plurality of output terminals for providing said signals from said first and second sets of input terminals to said input terminals of said programmable logic blocks.
Claim 7
Dependent Claim
67 words
A programmable interconnection system as in claim 1, further comprising: fourth, fifth and sixth interconnection circuits substantially identically to said first, second and third interconnection circuits respectively, said fourth and fifth circuits interconnecting respectively third and a fourth groups of programmable logic blocks, and said sixth interconnection circuit interconnecting said fourth and fifth interconnection circuits; and a seventh interconnection circuit interconnecting said third and sixth interconnection circuit.
Claim 8
Independent Claim
115 words
A method in a programmable interconnection system for interconnecting programmable logic blocks comprising: interconnecting a first group of programmable logic blocks using a first programmable interconnection circuit, said first programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said first group; interconnecting a second group of programmable logic blocks using a second programmable interconnection circuit, said second group of programmable logic blocks being separate and distinct from said first group of programmable logic blocks, said second programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said second group; and interconnecting said first and second programmable interconnection circuits using a third programmable interconnection circuit.
Claim 9
Independent Claim
115 words
A method in a programmable interconnection system for interconnecting programmable logic blocks comprising: interconnecting a first group of programmable logic blocks using a first programmable interconnection circuit, said first programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said first group; interconnecting a second group of programmable logic blocks using a second programmable interconnection circuit, said second group of programmable logic blocks being separate and distinct from said first group of programmable logic blocks, said second programmable interconnection circuit providing substantially the same delay between any two programmable logic blocks within said second group; and interconnecting said first and second programmable interconnection circuits using a third programmable interconnection circuit.
Claim 10
Dependent Claim
21 words
A method as in claim 7, wherein said first, second and third interconnection circuits are implemented in a volatile memory technology.
Claim 11
Dependent Claim
21 words
A method as in claim 7, wherein said first, second and third interconnection circuits are implemented in a non-volatile memory technology.
Claim 12
Dependent Claim
17 words
A method as in claim 7, wherein said programmable interconnection system is reprogrammable using in-system programmable techniques.
Claim 13
Dependent Claim
128 words
A method as in claim 7, wherein said programmable interconnection system being implemented in a programmable logic device having a plurality of input pins, said programmable logic blocks each having a plurality of input terminals and a plurlaity of output terminals, said step of interconnecting said first group of programmable logic blocks and said step of interconnecting said second group of programmable logic blocks each comprising the steps of: receiving signals from said output terminals of said programmable logic blocks at a first set of input terminals; receiving signals from said input pins at a second set of input terminals; and providing said signals from said first and second sets of input terminals to said input terminals of said programmable logic blocks at a plurality of output terminals.
Claim 14
Dependent Claim
81 words
A method as in claim 7, further comprising: interconnecting third and a fourth groups of programmable logic blocks using fourth and fifth interconnection circuits in the same manner as provided for said first and second groups of programmable logic blocks, said fourth and fifth interconnection circuits being substantially identical to said first and second interconnection circuits; interconnecting said fourth and fifth interconnection circuits using a sixth interconnection circuit; and interconnecting said third and sixth interconnection circuits using a seventh interconnection circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |