Programmable logic device

Claim 2

A programmable logic device including a plurality of groups of AND logic function gates, each AND logic function gate having a plurality of inputs, the AND logic function gates in each group having respective outputs coupled to inputs of a logic OR function output gate associated with that AND logic function gate group; each of said plurality of said AND logic function gate groups including individual output AND logic function gates having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that output AND logic function gate; each PLFG having one or more sets of logic input groups and including means for generating from each logic input group, an output logic signal comprising any logic function of that logic input group according to programmable control inputs applied to said first PLFG, each set of PLFGs coupled to supply PLFG outputs to the output AND logic function gate associated with that set of PLFGs; wherein the PLFGs in any set of PLFGs receive the same sets of logic input groups; and an output stage coupled to generate an output under control of outputs from said logic OR function gates, said output stage including a Boolean function generator (BLFG) comprising: means for generating an output signal representing any logic function of a plurality of first logic inputs according to second inputs to said BLFG; a plurality of logic cells having outputs coupled to said BLFG to supply said second inputs according to logic inputs to said logic cells; and a plurality of programmable OR logic function generators each having: an output coupled to supply one of said first logic inputs to said BLFG, a plurality of inputs coupled to respective outputs of a plurality of said logic OR function output gates, and control inputs to receive signals to programmably couple signals from said logic OR function output gates to said logic OR function generator output.

Claim 3

A programmable logic device according to claim 1, wherein in each PLFG there are 2 n programmable control inputs where n represents the number of logic inputs in each logic input group for that PLFG.

Claim 4

A programmable logic device according to claim 1, wherein neighboring ones of said AND logic function gate groups each comprises the same number of individual output AND logic function gates.

Claim 5

A programmable logic device according to claim 1, wherein said groups of AND logic function gates are disposed such that said array has a layout approximating a right-triangle with said output logic OR function gates and groups of AND logic function-gates disposed in columns along one side of said triangle.

Claim 6

A programmable logic device according to claim 1, wherein each logic input set comprises a logic input pair, and each PLFG includes for each logic input pair for that PLFG, an individual programmable cell connected to receive a first set of logic signals comprising minterms of said logic input pair, and having an output gate connected to receive inputs determined by said first set of logic signals and a second set of user programmable logic inputs to said PLFG.

Claim 7

A programmable logic device according to claim 1, wherein the programmable control inputs for each of the PLFGs are provided by values stored in a memory.

Claim 8

A programmable logic device according to claim 1, wherein the inputs of each said logic OR function generator are coupled to the same group of logic OR function output gates.

Claim 9

A programmable logic device according to claim 1, wherein each said logic cell includes selectable inputs comprising stored values.

Claim 10

A programmable logic device according to claim 1, wherein said BLFG output signal is coupled as an input to a store.

Claim 11

A programmable logic device according to claim 9, wherein said store is a clocked register stage.

Claim 12

A programmable logic device according to claim 10, wherein said clocked register stage has an output coupled to provide an input to said plurality of logic cells.

Claim 13

A programmable logic device according to claim 1, wherein said logic cells are coupled to a signal terminal to enable an external input to be coupled to said logic cells.

Claim 14

A programmable logic device according to claim 10, including a further programmable logic OR function generator having: a plurality of inputs coupled to respective outputs of a plurality of said logic OR function output gates, and control inputs to receive signals to programmably couple signals from said logic OR function output gates to an output of said further logic OR function generator; and a logic gate including inputs coupled to receive an output from said BLFG and an output from said further programmable logic OR function generator, said logic gate having an output coupled to an input of said clocked register stage.

Claim 15

A programmable logic device including a plurality of groups of AND logic function gates, each AND logic function gate having a plurality of inputs, the AND logic function gates in each group having respective outputs coupled to inputs of a logic OR function gate associated with that AND logic function gate group; each of a plurality of said groups of AND logic function gates including individual output AND logic function gates having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that group of AND logic function gates; each PLFG in a said set of PLFGs comprising logic gates coupled to receive the same set of logic input groups, and a group of programmable inputs for each respective logic input group, to generate, for each logic input group, a respective output determined according to said group of programmable inputs as any function of that particular logic input group, said outputs from said PLFGs in said set coupled as inputs to an AND logic function gate in said group of AND logic function gates operatively associated with that set of PLFGs; and circuitry to perform logic operations on outputs from said output logic OR function gates comprising: a plurality of Boolean function generators (BLFG) each having a plurality of first logic inputs coupled by signal selection circuitry comprising signal selectors having outputs coupled to supply respective ones of said first logic inputs to said BLFGs, each signal selector including a plurality of inputs coupled to outputs of at least some of said output logic OR function gates; each said BLFG comprising: logic circuitry to generate an output signal representing any function of said plurality of first logic inputs to said BLFG according to second inputs to said BLFG; and a plurality of logic cells having outputs coupled to said BLFG to supply said second inputs according to logic control inputs to said logic cells.

Claim 16

A programmable logic device including a plurality of groups of AND logic function gates, each AND logic function gate having a plurality of inputs, the AND logic function gates in each group having respective outputs coupled to inputs of a logic OR function gate associated with that AND logic function gate group; each of a plurality of said groups of AND logic function gates including individual output AND logic function gates having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that group of AND logic function gates; each PLFG in a said set of PLFGs comprising logic gates coupled to receive the same set of logic input groups, and a group of programmable inputs for each respective logic input group, to generate, for each logic input group, a respective output determined according to said group of programmable inputs as any function of that particular logic input group, said outputs from said PLFGs in said set coupled as inputs to an AND logic function gate in said group of AND logic function gates operatively associated with that set of PLFGs; and circuitry to perform logic operations on outputs from said output logic OR function gates comprising: a plurality of Boolean function generators (BLFG) each having a plurality of first logic inputs coupled by signal selection circuitry comprising signal selectors having outputs coupled to supply respective ones of said first logic inputs to said BLFGs, each signal selector including a plurality of inputs coupled to outputs of at least some of said output logic OR function gates; each said BLFG comprising: logic circuitry to generate an output signal representing any function of said plurality of first logic inputs to said BLFG according to second inputs to said BLFG; and a plurality of logic cells having outputs coupled to said BLFG to supply said second inputs according to logic control inputs to said logic cells.

Claim 17

A programmable logic device according to claim 14, wherein each said set of logic input groups comprises a set of logic input pairs, and each PLFG includes, for each logic input pair, a programmable cell having AND gates coupled to receive as inputs, respective minterms of said logic input pair, and respective programmable input signals.

Claim 18

A programmable logic device according to claim 14, wherein said signal selection circuitry comprises programmable OR logic function generators having outputs coupled to provide the respective first logic inputs to a said BLFG, each said programmable logic OR function generator including: a plurality of inputs coupled to respective outputs of a plurality of said logic OR function output gates, and control inputs to receive signals to programmably couple signals from said logic OR function output gates to said logic OR function generator output.

Claim 19

A programmable logic device according to claim 16 wherein the inputs of each said logic OR function generator are coupled to the same group of logic OR function output gates.

Claim 20

A programmable logic device according to claim 14, wherein each said logic cell includes selectable inputs comprising stored values.

Claim 21

A programmable logic device according to claim 14, including a plurality of clocked stores coupled to receive output signals from respective ones of at least some of said BLFGs.

Claim 22

A programmable logic device according to claim 14, wherein said logic cells are coupled to a signal terminal to enable an external input to be coupled to said logic cells.

Claim 23

A programmable logic device according to claim 19, including a further programmable logic OR function generator having: a plurality of inputs coupled to respective outputs of a plurality of said logic OR function output gates, and control inputs to receive signals to programmably couple signals from said logic OR function output gates to an output of said further logic OR function generator; and a logic gate coupled to receive as inputs an output from one of said BLFGs and an output from said further programmable logic OR function generator, said logic gate having an output coupled to an input of one of said clocked register stages.

Claim 24

A programmable logic device according to claim 14, further including a plurality of clocked stores each coupled to receive a said output signal from an individual BLFG, and to receive a clock signal to transfer an output from said clocked store as inputs to said logic cells coupled to that BLFG.

Claim 25

A programmable logic device according to claim 22, wherein at least some of said clocked stores are coupled to transfer an output to the logic cells of at least one other of said BLFGs.

Claim 26

A programmable logic device according to claim 22, including a plurality of externally accessible terminals coupled to logic inputs to the logic cells of respective BLFGs.

Claim 27

A programmable logic device including a plurality of groups of AND logic function gates each AND logic function gate having a plurality of inputs, the AND logic function gates in each group having respective outputs coupled to inputs of a logic OR function gate associated with that AND logic function gate group; each of a plurality of said groups of AND logic function gates including individual output AND logic function gates having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that group of AND logic function gates; each PLFG in a said set of PLFGs comprising logic gates coupled to receive the same set of logic input groups, and a group of programmable inputs for each respective logic input group, to generate, for each logic input group, a respective output determined according to said group of programmable inputs as any function of that particular logic input group, said outputs from said PLFGs in said set coupled as inputs to an AND logic function gate in said group of AND logic function gates operatively associated with that set of PLFGs; wherein at least some of said AND logic function gate groups comprise different numbers of logic input groups; and circuitry to perform logic operations controlled by outputs from said output logic OR function gates comprising: a plurality of Boolean function generators (BLFG) each having a plurality of first logic inputs coupled by programmable logic OR function generators to outputs of at least some of said output logic OR function gates; each said BLFG comprising: logic circuitry to generate an output signal representing any function of said plurality of first logic inputs to said BLFG according to second inputs to said BLFG; and a plurality of logic cells having outputs coupled to said BLFG to supply said second inputs according to logic control inputs to said logic cells; each said programmable logic OR function generator comprising: a plurality of inputs coupled to respective outputs of a plurality of said logic OR function output gates, and control inputs to receive signals to programmably couple signals from said logic OR function output gates to said logic OR function generator output; wherein a plurality of said BLFGs have outputs coupled to inputs of respective clocked stores, said clocked stores coupled to receive clock signals to transfer clocked store outputs as logic inputs to said logic cells of at least one BLFG, and to externally accessible outputs; and wherein the logic inputs to said logic cells also include selectable stored values.

Claim 28

A programmable logic device including a plurality of groups of AND logic function gates each AND logic function gate having a plurality of inputs, the AND logic function gates in each group having respective outputs coupled to inputs of a logic OR function gate associated with that AND logic function gate group; each of a plurality of said groups of AND logic function gates including individual output AND logic function gates having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that group of AND logic function gates; each PLFG in a said set of PLFGs comprising logic gates coupled to receive the same set of logic input groups, and a group of programmable inputs for each respective logic input group, to generate, for each logic input group, a respective output determined according to said group of programmable inputs as any function of that particular logic input group, said outputs from said PLFGs in said set coupled as inputs to an AND logic function gate in said group of AND logic function gates operatively associated with that set of PLFGs; wherein at least some of said AND logic function gate groups comprise different numbers of logic input groups; and circuitry to perform logic operations controlled by outputs from said output logic OR function gates comprising: a plurality of Boolean function generators (BLFG) each having a plurality of first logic inputs coupled by programmable logic OR function generators to outputs of at least some of said output logic OR function gates; each said BLFG comprising: logic circuitry to generate an output signal representing any function of said plurality of first logic inputs to said BLFG according to second inputs to said BLFG; and a plurality of logic cells having outputs coupled to said BLFG to supply said second inputs according to logic control inputs to said logic cells; each said programmable logic OR function generator comprising: a plurality of inputs coupled to respective outputs of a plurality of said logic OR function output gates, and control inputs to receive signals to programmably couple signals from said logic OR function output gates to said logic OR function generator output; wherein a plurality of said BLFGs have outputs coupled to inputs of respective clocked stores, said clocked stores coupled to receive clock signals to transfer clocked store outputs as logic inputs to said logic cells of at least one BLFG, and to externally accessible outputs; and wherein the logic inputs to said logic cells also include selectable stored values.

Claim 29

A programmable logic device according to claim 25, including at least one further programmable logic OR function generator having: a plurality of inputs coupled to respective outputs of a plurality of said logic OR function output gates, and control inputs to receive signals to programmably couple signals from said logic OR function output gates to an output of said further logic OR function generator; and a logic gate coupled to receive as inputs an output from one of said BLFGs and an output from said further programmable logic OR function generator, said logic gate having an output coupled to provide a said input to a said clocked store.