US5392293A — Built-in current sensor for IDDQ testing

Claim 1

Independent Claim 146 words

A method for detecting faults in an integrated circuit powered from a supply voltage V DD , composing the steps of: sinking current drawn by the integrated circuit during each interval that the circuit undergoes a logic transition; sensing the current drawn by the integrated circuit during intervals other than when the integrated circuit undergoes a logic transition; translating the sensed current to a corresponding sensed voltage; comparing the sensed voltage to a reference voltage representative of a quiescent current expected to be drawn by the integrated circuit during intervals other when the integrated circuit undergoes a logic transition; generating an indicating voltage in accordance with a difference between the sensed and reference voltages so as to indicate whether the quiescent current of the integrated circuit is above a expected quiescent current; and stabilizing the indicating voltage against variations in the supply voltage V DD .

Claim 2

Independent Claim 146 words

A method for detecting faults in an integrated circuit powered from a supply voltage V DD , composing the steps of: sinking current drawn by the integrated circuit during each interval that the circuit undergoes a logic transition; sensing the current drawn by the integrated circuit during intervals other than when the integrated circuit undergoes a logic transition; translating the sensed current to a corresponding sensed voltage; comparing the sensed voltage to a reference voltage representative of a quiescent current expected to be drawn by the integrated circuit during intervals other when the integrated circuit undergoes a logic transition; generating an indicating voltage in accordance with a difference between the sensed and reference voltages so as to indicate whether the quiescent current of the integrated circuit is above a expected quiescent current; and stabilizing the indicating voltage against variations in the supply voltage V DD .

Claim 3

Dependent Claim 50 words

The method according to claim 1 wherein the steps of sinking current and sensing the current drawn by the integrated circuit device are practiced by passing current from the integrated circuit through a diode coupled in series-aiding fashion between the integrated circuit and a negative bias voltage V ss .

Claim 4

Dependent Claim 24 words

The method according to claim 2 wherein the current passing in the diode is regulated to control a sensitivity of the current sensed thereby.

Claim 5

Dependent Claim 45 words

The method according to claim 3 wherein the current in the diode is regulated by the steps of: coupling a field effect transistor between a circuit ground and the junction of the diode and the integrated circuit; and controlling the current passing in the transistor.

Claim 6

Dependent Claim 166 words

A current sensor for measuring a quiescent current drawn by an integrated circuit, when supplied with a supply voltage V DD , to detect possible faults, comprising: a current sink and voltage transducer coupled to the integrated circuit for sinking current from the integrated circuit during intervals that the integrated circuit undergoes a logic transition and for providing a voltage in accordance with a quiescent current in the integrated circuit drawn during intervals other than when the integrated circuit undergoes a logic transition; a voltage comparator for comparing the voltage provided by the current sink and voltage transducer to a reference voltage representative of a prescribed quiescent current for the integrated circuit; a pre-amplifier stage coupled to the voltage comparator for providing an indicating voltage varying in accordance with a difference between the voltage provided by the current sink and voltage transducer and the reference voltage; and a stabilizing stage coupled to the pre-amplifer stage for stabilizing the indicating voltage against variations in the supply voltage.

Claim 7

Dependent Claim 166 words

A current sensor for measuring a quiescent current drawn by an integrated circuit, when supplied with a supply voltage V DD , to detect possible faults, comprising: a current sink and voltage transducer coupled to the integrated circuit for sinking current from the integrated circuit during intervals that the integrated circuit undergoes a logic transition and for providing a voltage in accordance with a quiescent current in the integrated circuit drawn during intervals other than when the integrated circuit undergoes a logic transition; a voltage comparator for comparing the voltage provided by the current sink and voltage transducer to a reference voltage representative of a prescribed quiescent current for the integrated circuit; a pre-amplifier stage coupled to the voltage comparator for providing an indicating voltage varying in accordance with a difference between the voltage provided by the current sink and voltage transducer and the reference voltage; and a stabilizing stage coupled to the pre-amplifer stage for stabilizing the indicating voltage against variations in the supply voltage.

Claim 8

Dependent Claim 38 words

The apparatus according to claim 5 wherein the current sink and voltage transducer comprises a diode coupled in series-aiding fashion with the integrated circuit between the supply voltage V DD and a negative bias voltage V ss .

Claim 9

Dependent Claim 118 words

The apparatus according to claim 6 wherein the voltage comparator comprises: first and second field effect transistors having their drain-to-source portions coupled in series-aiding fashion between a fixed voltage and circuit ground, the first transistor having its gate coupled to a junction between the transistors and the second transistor having its gate coupled to the current sink and voltage transducer; third and fourth field effect transistors having their drain-to-source portions coupled in series-aiding fashion between a fixed voltage and circuit ground, the third transistor having its gate coupled to the junction between the third and fourth transistors; and a second diode coupled between a gate of the fourth transistor and the negative voltage bias supply V ss .

Claim 10

Dependent Claim 21 words

The apparatus according to claim 7 further including means for regulating the current in each of the first and second diodes.

Claim 11

Dependent Claim 86 words

The apparatus according to claim 8 wherein the means for regulating the current in each of the first and second diodes comprises: a fifth field effect transistor having its source-to-drain portion coupled between a junction of the first diode and the integrated circuit, and circuit ground; a sixth field effect transistor having its source-to-drain portion coupled across the second diode; and a voltage divider network for supplying a portion of the supply voltage V DD to a gate of each of the fifth and sixth transistors.

Claim 12

Dependent Claim 63 words

The apparatus according to claim 9 wherein the voltage divider network comprises: seventh and eighth field effect transistors having their drain-to-source portions coupled in series-aiding fashion between the supply voltage V DD and circuit ground, each transistor having its gate coupled to the source thereof, the junction between the seventh and eighth transistors coupled to the gate of the fifth and sixth transistors.

Claim 13

Dependent Claim 71 words

The apparatus according to claim 5 wherein the stabilizing stage comprises: a pair of field effect transistors having their source-to-drain portions coupled in series-opposing fashion between the supply voltage V DD and circuit ground, a first one of the pair of transistors being supplied at its gate with the output of the pre-amplifier stage and the other transistor of the pair having its gate coupled to a junction between the transistors.

Claim 14

Dependent Claim 22 words

The apparatus according to claim 5 further including an amplifier-inverter for amplifying and inverting the indicating voltage stabilized by the stabilizing stage.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-02-20	1998-08-22	1999-02-21	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-02-20	2002-08-22	2003-02-21	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-02-20	2006-08-22	2007-02-21	$7700.00	Window Closed / Lapsed

Built-in current sensor for IDDQ testing

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